Digital Logic Design 5th Edition Solution Manual
Digital Design, 5th Edition Solution Manual
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1 SOLUTIONS MANUAL DIGITAL DESIGN WITH AN INTRODUCTION TO THE VERILOG HDL Fifth Edition M. MORRIS MANO Professor Emeritus California State University, Los Angeles MICHAEL D. CILETTI Professor Emeritus University of Colorado, Colorado Springs rev 02/14/2012 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 2 CHAPTER 1 1.1 Base-10: Octal: Hex: Base-12 16 17 20 21 10 11 14 15 1.2 (a) 32,768 18 22 12 16 19 23 13 17 20 24 14 18 21 25 15 19 (b) 67,108,864 3 22 23 24 25 26 27 30 31 16 17 18 19 1A 1B 20 21 26 27 28 29 30 32 33 34 35 36 1A 1B 1C 1D 1E 22 23 24 25 26 31 37 1F 27 32 40 20 28 (c) 6,871,947,674 (4310)5 = 4 * 5 + 3 * 5 + 1 * 51 = 58010 1.3 2 (198)12 = 1 * 122 + 9 * 121 + 8 * 120 = 26010 1.4 1.5 (435)8 = 4 * 82 + 3 * 81 + 5 * 80 = 28510 (345)6 = 3 * 62 + 4 * 61 + 5 * 60 = 13710 16-bit binary: 1111_1111_1111_1111 Decimal equivalent: 216 -1 = 65,53510 Hexadecimal equivalent: FFFF16 Let b = base (a) 14/2 = (b + 4)/2 = 5, so b = 6 (b) 54/4 = (5*b + 4)/4 = b + 3, so 5 * b = 52 – 4, and b = 8 (c) (2 *b + 4) + (b + 7) = 4b, so b = 11 1.6 (x – 3)(x – 6) = x2 –(6 + 3)x + 6*3 = x2 -11x + 22 Therefore: 6 + 3 = b + 1m, so b = 8 Also, 6*3 = (18)10 = (22)8 1.7 64CD16 = 0110_0100_1100_11012 = 110_010_011_001 _101 = (62315 )8 1.8 (a) Results of repeated division by 2 (quotients are followed by remainders): 43110 = 215(1); 107(1); 53(1); 26(1); 13(0); 6(1) Answer: 1111_10102 = FA16 3(0) 1(1) (b) Results of repeated division by 16: 43110 = 26(15); 1(10) (Faster) Answer: FA = 1111_1010 1.9 (a) 10110.01012 = 16 + 4 + 2 + .25 + .0625 = 22.3125 (b) 16.516 = 16 + 6 + 5*(.0615) = 22.3125 (c) 26.248 = 2 * 8 + 6 + 2/8 + 4/64 = 22.3125 (d) DADA.B16 = 14*163 + 10*162 + 14*16 + 10 + 11/16 = 60,138.6875 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 3 (e) 1010.11012 = 8 + 2 + .5 + .25 + .0625 = 10.8125 1.10 (a) 1.100102 = 0001.10012 = 1.916 = 1 + 9/16 = 1.56310 (b) 110.0102 = 0110.01002 = 6.416 = 6 + 4/16 = 6.2510 1.11 Reason: 110.0102 is the same as 1.100102 shifted to the left by two places. 1011.11 101 | 111011.0000 101 01001 101 1001 101 1000 101 0110 The quotient is carried to two decimal places, giving 1011.11 Checking: 1110112 / 1012 = 5910 / 510 ≅ 1011.112 = 58.7510 1.12 (a) 10000 and 110111 1011 +101 10000 = 1610 1011 x101 1011 1011 110111 = 5510 (b) 62h and 958h 2Eh +34 h 62h 1.13 0010_1110 0011_0100 0110_0010 = 9810 2Eh x34h B 38 2 8A 9 5 8h = 239210 (a) Convert 27.315 to binary: 27/2 = 13/2 6/2 3/2 ½ Integer Quotient 13 6 3 1 0 Remainder + + + + + ½ ½ 0 ½ ½ Coefficient a0 = 1 a1 = 1 a2 = 0 a3 = 1 a4 = 1 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 4 2710 = 110112 .315 x 2 .630 x 2 .26 x 2 .52 x 2 = = = = Integer 0 1 0 1 + + + + Fraction .630 .26 .52 .04 Coefficient a-1 = 0 a-2 = 1 a-3 = 0 a-4 = 1 .31510 ≅ .01012 = .25 + .0625 = .3125 27.315 ≅ 11011.01012 (b) 2/3 ≅ .6666666667 .6666_6666_67 x 2 .3333333334 x 2 .6666666668 x 2 .3333333336 x 2 .6666666672 x 2 .3333333344 x 2 .6666666688 x 2 .3333333376 x 2 Integer = 1 = 0 = 1 = 0 = 1 = 0 = 1 = 0 + + + + + + + + Fraction .3333_3333_34 .6666666668 .3333333336 .6666666672 .3333333344 .6666666688 .3333333376 .6666666752 Coefficient a-1 = 1 a-2 = 0 a-3 = 1 a-4 = 0 a-5 = 1 a-6 = 0 a-7 = 1 a-8 = 0 .666666666710 ≅ .101010102 = .5 + .125 + .0313 + ..0078 = .664110 .101010102 = .1010_10102 = .AA16 = 10/16 + 10/256 = .664110 (Same as (b)). 1.14 ` 1.15 (a) 0001_0000 1s comp: 1110_1111 2s comp: 1111_0000 (b) 0000_0000 1s comp: 1111_1111 2s comp: 0000_0000 (c) 1101_1010 1s comp: 0010_0101 2s comp: 0010_0110 (d) 1010_1010 1s comp: 0101_0101 2s comp: 0101_0110 (e) 1000_0101 1s comp: 0111_1010 2s comp: 0111_1011 (f) 1111_1111 1s comp: 0000_0000 2s comp: 0000_0001 (a) 25,478,036 9s comp: 74,521,963 10s comp: 74,521,964 (b) 63,325,600 9s comp: 36,674,399 10s comp: 36,674,400 (c) 25,000,000 9s comp: 74,999,999 10s comp: 75,000,000 (d) 00000000 9s comp: 99999999 10s comp: 100000000 1.16 15s comp: 16s comp: 1.17 C3DF 3C20 3C21 C3DF: 1100_0011_1101_1111 1s comp: 0011_1100_0010_0000 2s comp: 0011_1100_0010_0001 = 3C21 (a) 2,579 → 02,579 →97,420 (9s comp) → 97,421 (10s comp) 4637 – 2,579 = 2,579 + 97,421 = 205810 (b) 1800 → 01800 → 98199 (9s comp) → 98200 (10 comp) 125 – 1800 = 00125 + 98200 = 98325 (negative) Magnitude: 1675 Result: 125 – 1800 = 1675 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 5 (c) 4,361 → 04361 → 95638 (9s comp) → 95639 (10s comp) 2043 – 4361 = 02043 + 95639 = 97682 (Negative) Magnitude: 2318 Result: 2043 – 6152 = -2318 (d) 745 → 00745 → 99254 (9s comp) → 99255 (10s comp) 1631 -745 = 01631 + 99255 = 0886 (Positive) Result: 1631 – 745 = 886 1.18 1.19 Note: Consider sign extension with 2s complement arithmetic. (a) 0_10010 (b) 0_100110 1s comp: 1_01101 1s comp: 1_011001 with sign extension 2s comp: 1_01110 2s comp: 1_011010 0_10011 0_100010 Diff: 0_00001 (Positive) 1_111100 sign bit indicates that the result is negative Check:19-18 = +1 0_000011 1s complement 0_000100 2s complement 000100 magnitude Result: -4 Check: 34 -38 = -4 (c) 0_110101 (d) 1s comp: 1_001010 1s comp: 2s comp: 1_001011 2s comp: 0_001001 Diff: 1_010100 (negative) 0_101011 (1s comp) 0_101100 (2s complement) 101100 (magnitude) -4410 (result) 0_010101 1_101010 with sign extension 1_101011 0_101000 0_010011 sign bit indicates that the result is positive Result: 1910 Check: 40 – 21 = 1910 +9286 → 009286; +801 → 000801; -9286 → 990714; -801 → 999199 (a) (+9286) + (_801) = 009286 + 000801 = 010087 (b) (+9286) + (-801) = 009286 + 999199 = 008485 (c) (-9286) + (+801) = 990714 + 000801 = 991515 (d) (-9286) + (-801) = 990714 + 999199 = 989913 1.20 +49 → 0_110001 (Needs leading zero extension to indicate + value); +29 → 0_011101 (Leading 0 indicates + value) -49 → 1_001110 + 0_000001→ 1_001111 -29 → 1_100011 (sign extension indicates negative value) (a) (+29) + (-49) = 0_011101 + 1_001111 = 1_101100 (1 indicates negative value.) Magnitude = 0_010011 + 0_000001 = 0_010100 = 20; Result (+29) + (-49) = -20 (b) (-29) + (+49) = 1_100011 + 0_110001 = 0_010100 (0 indicates positive value) (-29) + (+49) = +20 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 6 (c) Must increase word size by 1 (sign extension) to accomodate overflow of values: (-29) + (-49) = 11_100011 + 11_001111 = 10_110010 (1 indicates negative result) Magnitude: 01_001110 = 7810 Result: (-29) + (-49) = -7810 1.21 +9742 → 009742 → 990257 (9's comp) → 990258 (10s) comp +641 → 000641 → 999358 (9's comp) → 999359 (10s) comp (a) (+9742) + (+641) → 010383 (b) (+9742) + (-641) →009742 + 999359 = 009102 Result: (+9742) + (-641) = 9102 (c) -9742) + (+641) = 990258 + 000641 = 990899 (negative) Magnitude: 009101 Result: (-9742) + (641) = -9101 (d) (-9742) + (-641) = 990258 + 999359 = 989617 (Negative) Magnitude: 10383 Result: (-9742) + (-641) = -10383 1.22 6,514 BCD: ASCII: ASCII: 0110_0101_0001_0100 0_011_0110_0_011_0101_1_011_0001_1_011_0100 0011_0110_0011_0101_1011_0001_1011_0100 1.23 0111 0110 1101 0110 0001 0011 0001 0001 0001 0100 1.24 0001 ( 791) 1000 (+658) 1001 0100 1001 (1,449) (a) 6 0 0 0 0 0 0 1 1 1 1 1.25 1001 0101 1110 0110 0100 3 0 0 0 1 1 1 0 0 0 1 (b) 1 0 0 1 0 1 1 0 1 1 0 1 0 1 0 0 0 1 0 0 1 0 Decimal 0 1 2 3 4 (or 0101) 5 6 7 (or 1001) 8 9 6 0 0 0 0 0 0 1 1 1 1 4 0 0 0 0 1 1 0 0 0 0 2 0 0 1 1 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 Decimal 0 1 2 3 4 5 6 (or 0110) 7 8 9 (a) 6,24810 (b) BCD: 0110_0010_0100_1000 Excess-3: 1001_0101_0111_1011 (c) (d) 2421: 6311: 0110_0010_0100_1110 1000_0010_0110_1011 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 1.26 7 6,248 9s Comp: 2421 code: 1s comp c: 6,2482421 1s comp c 3,751 0011_0111_0101_0001 1001_1101_1011_0001 (2421 code alternative #1) 0110_0010_0100_1110 (2421 code alternative #2) 1001_1101_1011_0001 Match Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 8 For a deck with 52 cards, we need 6 bits (25 = 32 < 52 < 64 = 26). Let the msb's select the suit (e.g., diamonds, hearts, clubs, spades are encoded respectively as 00, 01, 10, and 11. The remaining four bits select the "number" of the card. Example: 0001 (ace) through 1011 (9), plus 101 through 1100 (jack, queen, king). This a jack of spades might be coded as 11_1010. (Note: only 52 out of 64 patterns are used.) 1.27 1.28 G (dot) (space) B o o l e 11000111_11101111_01101000_01101110_00100000_11000100_11101111_11100101 1.29 Steve Jobs 1.30 73 F4 E5 76 E5 4A EF 62 73 73: F4: E5: 76: E5: 4A: EF: 62: 73: 0_111_0011 1_111_0100 1_110_0101 0_111_0110 1_110_0101 0_100_1010 1_110_1111 0_110_0010 0_111_0011 s t e v e j o b s 1.31 62 + 32 = 94 printing characters 1.32 bit 6 from the right 1.33 (a) 897 1.34 ASCII for decimal digits with even parity: 1.35 (b) 564 (0): 00110000 (4): 10110100 (8): 10111000 (1): (5): (9): (c) 871 10110001 00110101 00111001 (d) 2,199 (2): (6): 10110010 00110110 (3): (7): 00110011 10110111 (a) a b c a f b c g f g 1.36 a b a f g b f g Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 9 CHAPTER 2 2.1 (a) xyz x+y+z 000 001 010 011 100 101 110 111 0 1 1 1 1 1 1 1 (x + y + z)' x' 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 y' z' x' y' z' xyz (xyz) (xyz)' x' y' z' x' + y' + z' 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 000 001 010 011 100 101 110 111 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 (b) (c) xyz x + yz (x + y) (x + z) (x + y)(x + z) xyz x(y + z) xy xz xy + xz 000 001 010 011 100 101 110 111 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 000 001 010 011 100 101 110 111 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 (c) (d) xyz x y+z x + (y + z) (x + y) (x + y) + z xyz yz x(yz) xy 000 001 010 011 100 101 110 111 0 0 0 0 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 000 001 010 011 100 101 110 111 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 2.2 (xy)z 0 0 0 0 0 0 0 1 (a) xy + xy' = x(y + y') = x (b) (x + y)(x + y') = x + yy' = x(x +y') + y(x + y') = xx + xy' + xy + yy' = x (c) xyz + x'y + xyz' = xy(z + z') + x'y = xy + x'y = y (d) (A + B)'(A' + B')' = (A'B')(A B) = (A'B')(BA) = A'(B'B)A = 0 (e) (a + b + c')(a'b' + c) = aa'b' + ac + ba'b' + bc + c'a'b' + c'c = ac + bc +a'b'c' (f) a'bc + abc' + abc + a'bc' = a'b(c + c') + ab(c + c') = a'b + ab = (a' + a)b = b 2.3 (a) ABC + A'B + ABC' = AB + A'B = B Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 10 (b) x'yz + xz = (x'y + x)z = z(x + x')(x + y) = z(x + y) (c) (x + y)'(x' + y') = x'y'(x' + y') = x'y' (d) xy + x(wz + wz') = x(y +wz + wz') = x(w + y) (e) (BC' + A'D)(AB' + CD') = BC'AB' + BC'CD' + A'DAB' + A'DCD' = 0 (f) (a' + c')(a + b' + c') = a'a + a'b' + a'c' + c'a + c'b' + c'c' = a'b' + a'c' + ac' + b'c' = c' + b'(a' + c') = c' + b'c' + a'b' = c' + a'b' 2.4 (a) A'C' + ABC + AC' = C' + ABC = (C + C')(C' + AB) = AB + C' (b) (x'y' + z)' + z + xy + wz = (x'y')'z' + z + xy + wz =[ (x + y)z' + z] + xy + wz = = (z + z')(z + x + y) + xy + wz = z + wz + x + xy + y = z(1 + w) + x(1 + y) + y = x + y + z (c) A'B(D' + C'D) + B(A + A'CD) = B(A'D' + A'C'D + A + A'CD) = B(A'D' + A + A'D(C + C') = B(A + A'(D' + D)) = B(A + A') = B (d) (A' + C)(A' + C')(A + B + C'D) = (A' + CC')(A + B + C'D) = A'(A + B + C'D) = AA' + A'B + A'C'D = A'(B + C'D) (e) ABC'D + A'BD + ABCD = AB(C + C')D + A'BD = ABD + A'BD = BD 2.5 (a) x y Fsimplified F (b) x y Fsimplified F (c) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 11 x y z Fsimplified F (d) A B 0 Fsimplified F (e) x y z Fsimplified F (f) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 12 x y z F Fsimplified 2.6 (a) A B C F Fsimplified (b) x y z F Fsimplified (c) x y F Fsimplified Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 13 (d) w x y z F Fsimplified (e) A B C D Fsimplified = 0 F (f) w x y z F Fsimplified 2.7 (a) A B C D F Fsimplified Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 14 (b) w x y z F Fsimplified (c) A B C D F Fsimplified (d) A B C D F Fsimplified Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 15 (e) A B C D F Fsimplified 2.8 F' = (wx + yz)' = (wx)'(yz)' = (w' + x')(y' + z') FF' = wx(w' + x')(y' + z') + yz(w' + x')(y' + z') = 0 F + F' = wx + yz + (wx + yz)' = A + A' = 1 with A = wx + yz 2.9 (a) F' = (xy' + x'y)' = (xy')'(x'y)' = (x' + y)(x + y') = xy + x'y' (b) F' = [(a + c) (a + b')(a' + b + c')]' = (a + c)' + (a + b')' + (a' + b + c')' =a'c' + a'b + ab'c (c) F' = [z + z'(v'w + xy)]' = z'[z'(v'w + xy)]' = z'[z'v'w + xyz']' = z'[(z'v'w)'(xyz')'] = z'[(z + v + w') +( x' + y' + z)] = z'z + z'v + z'w' + z'x' + z'y' +z' z = z'(v + w' + x' + y') 2.10 2.11 (a) F1 + F2 = Σ m1i + Σm2i = Σ (m1i + m2i) (b) F1 F2 = Σ mi Σmj where mi mj = 0 if i ≠ j and mi mj = 1 if i = j (a) F(x, y, z) = Σ(1, 4, 5, 6, 7) (b) F(a, b, c) = Σ(0, 2, 3, 7) F = xy + xy' + y'z 2.12 F = bc + a'c' xyz F abc F 000 001 010 011 100 101 110 111 0 1 0 0 1 1 1 1 000 001 010 011 100 101 110 111 1 0 1 1 0 0 0 1 A = 1011_0001 B = 1010_1100 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 16 (a) (b) (c) (d) (e) 2.13 A AND B = 1010_0000 A OR B = 1011_1101 A XOR B = 0001_1101 NOT A = 0100_1110 NOT B = 0101_0011 (a) u x y z (u + x') Y = [(u + x')(y' + z)] (y' + z) (b) u x y x Y = (u xor y)' + x (u xor y)' (c) u x y z (u'+ x') Y = (u'+ x')(y + z') (y + z') (d) u x y z u(x xor z) Y = u(x xor z) + y' y' (e) u x y z u yz Y = u + yz +uxy uxy (f) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 17 u x y Y = u + x + x'(u + y') x'(u + y') (u + y') 2.14 (a) x y z F =xy + x'y' + y'z (b) x y z F = xy + x'y' + y'z = (x' + y')' + (x + y)' + (y + z')' (c) x y z F = xy + x'y' + y'z = [(xy)' (x'y')' (y'z)']' (d) x y z F = xy + x'y' + y'z = [(xy)' (x'y')' (y'z)']' Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 18 (e) x y z F = xy + x'y' + y'z = (x' + y')' + (x + y)' + (y + z')' 2.15 (a) T1 = A'B'C' + A'B'C + A'BC' = A'B'(C' + C) +A'C'(B' + B) = A'B' +A'C' = A'(B' + C') (b) T2 =T1' = A'BC + AB'C' + AB'C + ABC' + ABC = BC(A' + A) + AB'(C' + C) + AB(C' + C) = BC + AB' + AB = BC + A(B' + B) = A + BC ∑ (3, 5, 6, 7) = Π (0,1, 2, 4) T1 = A'B'C' + A'B'C + A'BC' A'B' A'C' T2 = A'BC + AB'C' + AB'C + ABC' + ABC AC' AC T1 = A'B' A'C' = A'(B' + C') BC T2 =AC' + BC + AC = A+ BC 2.16 (a) F(A, B, C) = A'B'C' + A'B'C + A'BC' + A'BC + AB'C' + AB'C + ABC' + ABC = A'(B'C' + B'C + BC' + BC) + A((B'C' + B'C + BC' + BC) = (A' + A)(B'C' + B'C + BC' + BC) = B'C' + B'C + BC' + BC = B'(C' + C) + B(C' + C) = B' + B = 1 (b) F(x1, x2, x3, ..., xn) = Σmi has 2n/2 minterms with x1 and 2n/2 minterms with x'1, which can be factored and removed as in (a). The remaining 2n-1 product terms will have 2n-1/2 minterms with x2 and 2n-1/2 minterms with x'2, which and be factored to remove x2 and x'2. continue this process until the last term is left and xn + x'n = 1. Alternatively, by induction, F can be written as F = xnG + x'nG with G = 1. So F = (xn + x'n)G = 1. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 19 2.17 (a) F = (b + cd)(c + bd) bc + bd + cd + bcd = Σ(3, 5, 6, 7, 11, 14, 15) F' = Σ(0, 1, 2, 4, 8, 9, 10, 12, 13) F = Π(0, 1, 2, 4, 8, 9, 10, 12, 13) abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 F 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 1 (b) (cd + b'c + bd')(b + d) = bcd + bd' + cd + b'cd = cd + bd' = Σ (3, 4, 7, 11, 12,14, 15) = Π (0, 1, 2, 5, 6, 8, 9, 10, 13) abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 F 0 0 0 1 1 0 0 1 0 0 0 1 1 0 1 1 (c) (c' + d)(b + c') = bc' + c' + bd + c'd = (c' + bd) = Σ (0, 1, 4, 5, 7, 8, 12, 13, 15) F = Π (2, 3, 6, 9, 10, 11, 14) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 20 (d) bd' + acd' + ab'c + a'c' = Σ (0, 1, 4, 5, 10, 11, 14) F' = Σ (2, 3, 6, 7, 8, 9, 12, 13, 15) F = Π (02, 3, 6, 7, 8, 12, 13, 15) abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 F 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 21 2.18 (a) (b) wx y z F 00 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 10 0 0 10 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 11 1 1 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 1 x y' z x' y' z w' x y w x' y w x y F = xy'z + x'y'z + w'xy + wx'y + wxy F = Σ(1, 5, 6, 7, 9, 10 11, 13, 14, 15 ) 5 - Three-input AND gates 2 - Three-input OR gates Alternative: 1 - Five-input OR gate 4 - Inverters F (c) F = xy'z + x'y'z + w'xy + wx'y + wxy = y'z + xy + wy = yʹ′z + y(w + x) (d) F = y'z + yw + yx) = Σ(1, 5, 9, 13 , 10, 11, 13, 15, 6, 7, 14, 15) = Σ(1, 5, 6, 7, 9, 10, 11, 13, 14, 15) (e) y' z x w y F 1 – Inverter, 2 – Two-input AND gates, 2 – Two-input OR gates Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 22 2.19 F = B'D + A'D + BD 2.20 ABCD ABCD ABCD -B'-D 0001 = 1 0011 = 3 1001 = 9 1011 = 11 A'--D 0001 = 1 0011 = 3 0101 = 5 0111 = 7 -B-D 0101 = 5 0111 = 7 1101 = 13 1111 = 15 F = Σ(1, 3, 5, 7, 9, 11,13, 15) = Π(0, 2, 4, 6, 8, 10, 12, 14) (a) F(A, B, C, D) = Σ(2, 4, 7, 10, 12, 14) F'(A, B, C, D) = Σ(0, 1, 3, 5, 6, 8, 9, 11, 13, 15) (b) F(x, y, z) = Π(3, 5, 7) F' = Σ(3, 5, 7) 2.21 2.22 (a) F(x, y, z) = Σ(1, 3, 5) = Π(0, 2, 4, 6, 7) (b) F(A, B, C, D) = Π(3, 5, 8, 11) = Σ(0, 1, 2, 4, 6, 7, 9, 10, 12, 13, 14, 15) (a) (u + xw)(x + u'v) = ux + uu'v + xxw + xwu'v = ux + xw + xwu'v = ux + xw = x(u + w) = ux + xw (SOP form) = x(u + w) (POS form) (b) x' + x(x + y')(y + z') = x' + x(xy + xz' + y'y + y'z') = x' + xy + xz' + xy'z' = x' + xy +xz' (SOP form) = (x' + y + z') (POS form) 2.23 (a) B'C +AB + ACD A B C D F Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 23 (b) (A + B)(C + D)(A' + B + D) A B C D F (c) (AB + A'B')(CD' + C'D) A B C D F (d) A + CD + (A + D')(C' + D) A B C D F 2.24 x ⊕ y = x'y + xy' and (x ⊕ y)' = (x + y')(x' + y) Dual of x'y + xy' = (x' + y)(x + y') = (x ⊕ y)' 2.25 (a) x| y = xy' ≠ y | x = x'y (x | y) | z = xy'z' ≠ x | (y | z) = x(yz')' = xy' + xz Not commutative Not associative Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 24 (b) (x ⊕ y) = xy' + x'y = y ⊕ x = yx' + y'x Commutative (x ⊕ y) ⊕ z = ∑(1, 2, 4, 7) = x ⊕ (y ⊕ z) Associative 2.26 NAND (Positive logic) Gate xy z xy z xy z LL LH HL HH H H H L 00 01 10 11 1 1 1 0 11 10 01 00 0 0 0 1 NOR (Positive logic) Gate 2.27 NOR (Negative logic) NAND (Negative logic) xy z xy z xy z LL LH HL HH H L L L 00 01 10 11 1 0 0 0 11 10 01 00 0 1 1 1 f1 = a'b'c' + a'bc' + a'bc + ab'c' + abc = a'c' + bc + a'bc' + ab'c' f2 = a'b'c' + a'b'c + a'bc + ab'c' + abc = a'b' + bc + ab'c' a' b' a' a' b c' a' b c a' b c a b c a' b' c a' b c a b' c a' c' b f1 f2 c a' b c' a b' c' a' b' b f1 f2 c a b' c' Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 2.28 25 (a) y = a(bcd)'e = a(b' + c' + d')e y = a(b' + c' + d')e = ab'e + ac'e + ad'e = Σ( 17, 19, 21, 23, 25, 27, 29) a bcde y a bcde y 0 0000 0 0001 0 0010 0 0011 0 0100 0 0101 0 0110 0 0111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 0 1000 0 1001 0 1010 0 1011 0 1100 0 1101 0 1110 0 1111 1 1000 1 1001 1 1010 1 1011 1 1100 1 1101 1 1110 1 1111 (b) y1 = a ⊕ (c + d + e)= a'(c + d +e) + a(c'd'e') = a'c + a'd + a'e + ac'd'e' y2 = b'(c + d + e)f = b'cf + b'df + b'ef y1 = a (c + d + e) = a'(c + d +e) + a(c'd'e') = a'c + a'd + a'e + ac'd'e' y2 = b'(c + d + e)f = b'cf + b'df + b'ef a'-c--001000 = 8 001001 = 9 001010 = 10 001011 = 11 a'--d-000100 = 8 000101 = 9 000110 = 10 000111 = 11 a'---e000010 = 2 000011 = 3 000110 = 6 000111 = 7 001100 = 12 001101 = 13 001110 = 14 001111 = 15 001100 = 12 001101 = 13 001110 = 14 001111 = 15 001010 = 10 001011 = 11 001110 = 14 001111 = 15 011000 = 24 011001 = 25 011010 = 26 011011 = 27 010100 = 20 010101 = 21 010110 = 22 010111 = 23 010010 = 18 010011 = 19 010110 = 22 010111 = 23 011100 = 28 011101 = 29 011110 = 30 011111 = 31 011100 = 28 011101 = 29 011110 = 30 011111 = 31 011010 = 26 011001 = 27 011110 = 30 011111 = 31 a-c'd'e'100000 = 32 100001 = 33 110000 = 34 110001 = 35 -b' c--f -b' -d-f -b' --ef 001001 = 9 001011 = 11 001101 = 13 001111 = 15 101001 = 41 101011 = 43 101101 = 45 101111 = 47 001001 = 9 001011 = 11 001101 = 13 001111 = 15 101001 = 41 101011 = 43 101101 = 45 101111 = 47 000011 = 3 000111 = 7 001011 = 11 001111 = 15 100011 = 35 100111 = 39 101011 = 51 101111 = 55 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 26 y1 = Σ (2, 3, 6, 7, 8, 9, 10 ,11, 12, 13, 14, 15, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35 ) y2 = Σ (3, 7, 9, 13, 15, 35, 39, 41, 43, 45, 47, 51, 55) ab cdef y1 y2 ab cdef y1 y2 ab cdef y1 y2 ab cdef y1 y2 00 0000 00 0001 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 01 0000 01 0001 01 0010 01 0011 01 0100 01 0101 01 0110 01 0111 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 10 0000 10 0001 10 0010 10 0011 10 0100 10 0101 10 0110 10 0111 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 1 11 0000 11 0001 11 0010 11 0011 11 0100 11 0101 11 0110 11 0111 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 00 1000 00 1001 00 1010 00 1011 00 1100 00 1101 00 1110 00 1111 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 1 01 1000 01 1001 01 1010 01 1011 01 1100 01 1101 01 1110 01 1111 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 10 1000 10 1001 10 1010 10 1011 10 1100 10 1101 10 1110 10 1111 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 27 Chapter 3 3.1 x y yz 00 01 m0 0 m1 m3 m2 m5 m7 m6 1 00 01 m0 1 1 y yz x 10 1 m4 x 11 0 x 1 00 01 m0 0 m1 1 1 1 m7 m5 m7 m6 1 1 1 y yz 00 m2 1 m5 x 10 m3 1 m4 x 11 m2 z F = z' + xy' y yz m3 1 z F = xy' + x'z' x 10 m1 1 m4 1 11 01 m0 m1 m4 m5 0 m6 1 x 11 1 m2 1 1 m7 1 z F = x' + y'z 10 m3 m6 1 z F = x'z + yz + x'y 3.2 x 00 0 x y yz 1 m0 1 m4 m1 m5 11 m3 1 m7 1 00 01 11 m0 m1 m3 m4 m5 m7 0 x 1 0 m6 x 1 x 10 m2 1 1 1 m4 m5 1 x 11 m3 m7 1 m6 1 1 z F = y + x'z y 00 1 10 m2 1 yz 01 m0 m1 m4 m5 11 m3 1 10 m2 1 m7 1 1 m6 1 1 z z F = xy' + x'y (c) m1 0 1 m6 01 m0 (b) y yz 00 m2 1 y yz x 10 z F = x'y' + xz (a) x 01 F=y+z (d) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 28 x y yz 00 m0 0 11 10 m1 m3 m2 m5 m7 m6 1 m4 x 01 1 x 1 00 01 11 m0 m1 m3 m4 m5 m7 0 1 1 y yz x 10 m2 1 1 1 m6 1 1 1 z z F = z' F=x+yz (e) (f) 3.3 x 00 0 x y yz 1 m0 1 m4 m3 m2 m5 m7 m6 1 1 1 x 0 01 m1 11 m3 1 m4 m5 1 m7 1 x m2 1 1 m4 m1 1 m5 11 m3 m7 1 1 x 10 m2 1 m6 z F = x'y' + yz + x'yz' F = x' + yz yz 00 1 01 11 m0 m1 m3 m4 m5 m7 10 m2 1 1 m6 1 z F = x'yz + xy'z' + xy'z F = x'yz + xy' z F = x'y + yz' + y'z' F = = x' y + z' (c) m0 01 0 1 m6 00 (b) 10 1 y yz 0 y 00 1 x 10 m1 yz m0 x 11 z F =xy + x'y'z' + x'yz' F = xy + x' z' (a) x 01 (d) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 29 3.4 AB CD y yz 0 x 1 00 m0 01 m1 11 m3 1 10 m2 1 m4 m5 m7 m6 1 11 A 10 (a) AB F=y m5 m7 m12 m13 m15 m14 m8 m9 m11 m10 1 C 00 00 01 11 A 10 01 11 m0 m1 m3 m4 m5 m7 m2 1 m6 1 m15 m14 m8 m9 m11 m10 1 B 1 1 1 11 w 10 01 11 m0 m1 m3 m4 m5 m7 B 10 m2 1 1 m6 m12 m13 m15 m14 m8 m9 m11 m10 1 1 D (c) 1 y 00 01 m13 m6 1 yz 00 m12 1 wx 10 m2 D F = BCD + A' BD' (b) CD 10 m3 z 11 m1 m4 01 1 01 m0 00 x C 00 1 x 1 z F =CD + ABD + ABC (d) F = w'x'y +wx wx yz y 00 01 m0 11 m1 wx 10 m3 y 00 m2 00 01 11 10 m0 m1 m3 m2 m4 m5 m7 m6 m15 m14 00 m4 m5 m7 m6 01 01 m12 11 w yz m13 1 m15 1 m8 x m14 m12 1 m9 11 m11 10 w m10 1 m8 10 z m9 x 1 m11 1 m10 1 F = wz' + xy'w 1 z F = wx + wyz (e) m13 1 (f) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 30 3.5 y yz wx 00 m0 01 m1 00 11 AB 10 m3 m4 m5 m0 11 m6 m13 1 m15 1 w m9 m11 m5 11 A m10 m13 1 m15 m14 1 m9 B 1 m11 z m10 D F =xz' + w'y'z+ wxy (b) y yz 00 01 m0 m1 00 11 m3 1 m4 01 1 1 11 m8 m2 m0 m6 1 01 x m14 m9 1 (c) z F = z + xw' A m10 m2 m5 m7 m6 1 1 m13 1 1 m15 1 m8 1 10 m3 11 m11 10 11 m1 1 m12 1 01 1 m4 1 m15 1 C 00 00 m7 m13 F = AC' + ABC' + ABD' CD AB 10 1 m5 m12 w m6 10 (a) wx 1 m7 1 m8 10 m2 1 m12 1 10 m3 01 x m14 1 m8 m1 11 1 m4 1 m12 01 00 m7 1 00 m2 1 01 C CD m9 B m14 1 m11 m10 10 1 D F =BD + A'B + B' D' or = BD + B'D' + A'D' (d) 3.6 AB CD C 00 00 01 11 A 10 (a) m0 1 m4 01 11 m1 m3 m2 m5 m7 m6 1 1 1 m13 m15 m14 m8 m9 m11 m10 1 1 yz 1 D F = B' D' +A'BD + ABC' y 00 00 01 m12 1 wx 10 B 11 w 10 (b) 01 m0 m1 m4 m5 1 1 1 11 m3 1 10 m2 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 1 x 1 z F = xy' +x'z + wx'y Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 31 AB CD C 00 m0 01 m1 00 11 m3 m4 m5 m12 m0 m6 m15 B m14 m9 A m10 1 1 m6 1 m15 m14 m11 m10 B 1 m8 m9 10 1 D F = C'D + A'BD + A'B'C' (d) F = A'BC' + B'C'D + ACD + AB'C m2 m7 m13 D (c) 10 m3 1 11 m11 1 11 1 m5 m12 1 m8 m1 01 11 10 01 1 m4 1 m13 C 00 00 m7 1 CD m2 1 01 A AB 10 3.7 wx yz y 00 m0 01 m1 00 m4 m5 11 AB m8 m9 z F = z + x'y 00 01 m1 m3 m5 m7 1 m12 m13 11 (c) m9 1 wx m11 1 m15 m14 1 B 1 m11 m10 1 1 y 01 m1 11 m3 10 m2 00 m4 01 m14 m6 D F = AD' + C'D + BCD' m0 1 m15 m7 1 m9 1 00 m2 1 m2 yz m6 1 m8 1 m8 10 10 1 01 m13 (b) 11 1 m4 10 1 C 00 m5 m12 A m10 10 m3 1 11 1 CD A x 11 1 m4 m14 m11 (a) m1 01 1 1 m0 m6 m15 10 01 00 1 1 C 00 m0 1 m7 m13 CD m2 1 1 m12 AB 10 m3 1 01 w 11 B m12 1 m10 m5 1 m13 11 w 1 m8 1 10 D F = B'D' + AC + A'BD + CD (or B'C) (d) m7 1 m9 m6 1 m15 1 m14 1 m11 x 1 m10 z F = xw' + xz + xy Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 32 3.8 (a) F(x, y, z) = Σ(3, 5, 6, 7) x 00 0 x y yz 1 01 11 m0 m1 m3 m4 m5 m7 1 1 1 10 m2 m6 1 z (b) F = Σ(1, 3, 5, 9, 12, 13, 14) AB CD C 00 00 01 11 A 10 01 m0 m1 m4 m5 1 1 11 m3 1 10 m2 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 B 1 D (c) F = Σ(0, 1, 2, 3, 11, 12, 14, 15) y wx 00 00 01 11 w 10 m0 1 m4 01 m1 1 11 m3 1 10 m2 1 m5 m7 m12 m13 m15 m14 m8 m9 m11 m10 1 m6 1 1 x 1 z Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 33 (d) F = Σ(3, 4, 5, 7, 11, 12) CD AB C 00 00 01 11 A 10 m0 m4 1 01 m1 m5 1 11 m3 m7 10 m2 1 m6 1 m12 m13 m15 m14 m8 m9 m11 m10 1 1 B D 3.9 yz wx y 00 m0 00 01 01 m1 m3 m2 m5 m7 m6 1 1 1 m13 11 1 m8 01 m3 m4 m5 m7 m12 m13 1 1 m11 A m10 1 1 m9 (b) CD 11 m0 m1 m3 m4 m5 m7 00 1 11 m13 1 m8 10 1 wx 10 1 1 m1 m4 m5 1 D m10 m3 1 B m12 w 1 m8 10 m13 m6 m15 1 m9 1 10 m2 1 m7 1 11 m11 (c) m0 11 01 1 1 01 00 1 m14 y 00 m6 m15 m9 yz m2 1 m12 A Essential: B'D', AC, A'BD Non-essential: CD, B'C F = B'D' + AC + A'BD + (CD OR B'C) C 01 1 D Essential: xz, x'z' Non-essential: w'x, w'z' F = xz + x'z' + (w'x or w'z') 01 m10 1 (a) 00 1 m11 1 B m14 1 m8 10 1 m6 m15 11 1 10 m2 1 z AB 11 m1 01 x m14 1 m9 C 00 00 1 m15 CD m0 1 m12 10 AB 10 1 m4 w 11 1 m11 1 m14 x 1 m10 1 z (d) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 34 Essential: BC', AC, A'B'D Non-Essential: A'B F = BC' + AC + A'B'D AB Essential: wy', xy, w'x'z F = wy' + xy + w'x'z CD C 00 01 m0 00 11 m1 1 m3 m2 m7 m6 1 m4 m5 m12 m13 01 A m8 10 01 m5 m12 m13 01 m2 m7 m6 1 1 1 m15 11 m11 m8 1 x m14 1 w m10 1 10 m3 1 m4 10 m9 m11 m10 1 1 z D 11 m1 1 B m14 1 m9 1 y 00 00 1 m15 1 yz m0 1 1 11 wx 10 Essential: BD, B'C', C'D F = BD + B'C' + C'D Essential: x'z', w'y'z, xyz F = x'z' + w'y'z + xyz 3.10 wx yz y 00 m0 00 01 m1 m3 m2 m5 m7 m6 1 m12 m8 10 m13 1 m15 m9 1 m11 1 C 00 00 01 m1 m3 m5 m7 m14 1 m12 1 m13 A m15 1 m8 1 10 m9 m11 1 1 z 1 m6 1 11 m10 10 m2 1 01 x 11 1 m4 1 1 CD m0 1 01 11 AB 10 1 m4 w 11 m14 m10 1 D F = Σ(0, 2, 5, 7, 8, 10, 12, 13, 14, 15) Essential: xz, wx, x'z' F = xz + wx + x'z' (a) F = Σ(0, 2, 3, 5, 7, 8, 10, 11, 14, 15) Essential: AC, B'D', CD, A'BD F = AC + B'D' + CD + A'BD B 1 (b) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 35 CD AB C 00 01 m0 m1 m4 m5 00 11 m3 1 01 1 m13 1 A m8 m9 m11 10 m13 m8 m9 10 AB (c) CD m0 00 01 m1 1 m4 11 m3 1 m5 m12 m13 wx 10 m9 1 m11 B m10 1 (d) y 00 01 m1 1 01 m14 yz m4 F(A, B, C, D) = S(0, 1, 3, 7 8, 9, 10,13,15) Essential: B'C', AB'D' Non-essential: ABD, A'CD, BCD F = B'C' + AB'D' +A'CD +ABD (e) 00 11 m2 m7 m6 1 1 1 m13 1 m15 11 w 10 m3 1 m5 m12 1 1 m0 m2 D m6 m15 1 m8 10 1 11 m10 1 F = Σ(0, 1, 4, 5, 6, 7, 9, 11, 14, 15) Essential: w'y', xy, wx'z Non-essential: wx, x'y'z, w'wz, w'x'z F = w'y' + xy + wx'z 1 m7 01 A C 00 1 m11 1 x m14 z F = Σ(1, 3, 4, 5, 10, 11, 12, 13, 14, 15) Essential: AC, BC', A'B'D Non-essential: AB, Aʹ′Bʹ′D, Bʹ′CD, Aʹ′Cʹ′D F = AC + BCʹ′ + Aʹ′Bʹ′D 1 m15 D m6 1 1 w 1 m2 m7 1 11 m10 1 m5 m12 1 10 m3 1 1 B 11 m1 1 01 m14 1 01 m4 m6 m15 1 y 00 00 1 m7 yz m0 m2 1 m12 11 wx 10 1 m14 x 1 m8 m9 m11 10 m10 1 z F = S(0, 1, 2, 4, 5, 6, 7, 10, 15) Essential: w'y', w'z', xyz, x'yz' Non-Essential: w'x F = w'y' + w'z' + xyz + x'yz' (f) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 36 3.11 (a) F(w, x, y, z) = ∑ (0, 1, 2, 5, 8, 10, 13) y yz wx 00 m0 00 01 m1 1 m4 wx 10 m3 m2 m7 m6 1 m5 01 1 m13 11 m8 10 m9 m15 x m14 m11 w m10 1 F = x'z' + w'x'y' + xy'z 11 m1 m3 m4 m5 m7 1 m8 m6 1 m13 1 10 10 m2 1 11 1 01 m0 m12 z 00 01 1 w y yz 00 1 m12 11 m15 1 m9 m11 1 1 m14 x 1 m10 1 z F' = yz + xy + xz' + wx'z F = (y' + z')(x' + y')(x' + z)(w' +x + z') Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 3.12 37 (a) F = Π(1, 3, 5, 7, 13, 15) F' = A'D + B'D F = (A + Dʹ′)(Bʹ′ + Dʹ′) F = C'D' + AB' + CD' AB CD C 00 m0 01 m1 00 m4 m7 0 m12 m6 0 m13 m15 0 m8 m2 0 m5 11 10 m3 0 01 A 11 B m14 0 m9 m11 m10 10 D (b) F = Π(1, 3, 6, 9, 11, 12, 14) F' = B'D + BCD' + ABD' F = (B + D')(B' + C' + D)(A' + B' + D) F = BD + B'D' + A'C'D' AB CD C 00 00 01 11 A 10 01 11 m1 m4 m5 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 0 m3 10 m0 0 0 0 0 m2 0 B 0 D Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 38 3.13 (a) F = x'z' + y'z' + yz' + xy = x'z' + z' + xy = z' + xy x y yz 00 m0 0 11 m1 m3 10 m2 1 m4 x 01 1 m5 1 m7 m6 1 1 1 z F' = x'z + y'z F = (x + z')(y + z') (b) F = ACD' + C'D + AB' + ABCD AB CD C 00 m0 01 m1 00 m4 m5 m2 m7 m6 1 m12 m13 11 m15 1 m8 10 10 m3 1 01 A 11 m9 1 1 m11 1 1 m14 B 1 m10 1 D F = AC + AB' + C'D F' = A'C + A'D' + BC'D' F = (A + C')(A + D)(B'+C + D) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 39 (c) F = (A' + B + D')(A' + B' + C')(A' + B' + C)(B' + C + D') F' = AB'D + ABC + ABC' + BC'D AB CD C 00 m0 01 m1 00 m4 m5 10 m3 0 01 m2 0 m7 m6 0 m12 11 A 11 m13 0 m8 m15 0 m9 m14 0 B 0 m11 m10 10 D F' = AB + BC'D F = (A' + B')(B' + C + D') F = A'D' + A'BC + AB' AB CD C 00 m0 00 m4 11 m5 m13 10 m2 0 m7 m15 0 m11 1 1 m6 1 0 m9 1 m3 0 0 m8 11 0 1 m12 10 m1 1 01 A 01 1 1 m14 B 0 m10 1 D Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 40 (d) F = BCD' + ABC' + ACD AB CD C 00 01 11 AB 10 m0 m1 m3 m2 m4 m5 m7 m6 m12 m13 m15 m14 C 00 m0 00 00 01 1 m8 1 01 B m9 11 0 0 10 m3 m2 0 0 m7 0 m13 m6 0 m15 m14 11 m11 10 m1 m5 m12 1 01 0 m4 1 11 A CD A m10 1 B 0 m8 10 m9 0 m11 m10 0 D 0 D F' = A'C' + A'D + B'C' + A'B' + ACD'\ F = (A + C)(A + D') (B + C)(A + B)(A' +C' + D) 3.14 AB CD C 00 m0 00 01 m1 1 m4 11 m3 m5 m7 m0 m6 01 m1 11 m3 m13 m15 m4 m14 B m9 m11 10 m10 1 1 m5 11 A m13 m9 0 m15 0 0 m6 0 0 m8 10 m7 0 m12 1 10 m2 0 01 11 m8 C 00 00 1 m12 CD m2 1 01 A AB 10 0 m14 B 0 m11 m10 0 D D SOP form (using 1s): F = A'BC'D + AB'CD + A'B'C' + ACD' F = A'B'C' + A'C'D + AB'C + ACD' POS form (using 0s): F' = AC' + A'C + A'C'D' + ABD F = (A' + C)(A + C')(A + C + D)(A' + B' + D') Alternative POS: F' = AC' + A'C + A'C'D' + BCD F = (A' + C)(A + C')(A + C + D)(B' + C' + D') Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 41 3.15 AB CD C 00 m0 00 x 00 m0 0 11 m1 1 m4 x 01 m3 1 m7 1 A m6 1 x m3 m2 m5 m7 m6 x 1 m13 11 x m8 m9 CD m0 11 m1 m3 00 m4 m5 m2 m0 11 m15 1 m8 1 m9 10 B A m10 m5 m7 m15 m14 m9 m11 m10 x B 1 D 3.16 x m13 1 D F = BC + CD + ABD' + A'BD F = Σ(3, 5, 6, 7, 11, 12, 14, 15) 10 m2 m6 1 m8 10 m3 1 11 x m1 11 1 m12 1 m11 x 01 m14 01 x m4 1 C 00 m6 1 m13 m10 x CD 00 m7 1 m12 A AB 10 x 01 m11 F = A'D' + B'D' + BCD' + ABC'D F = Σ(0, 2, 4, 6, 8, 10, 13, 14) C 01 B 1 D F=1 F = Σ(0,1, 2, 3, 4, 5, 6, 7) 00 m14 1 z AB m15 1 10 1 10 m1 x m12 m2 x m5 1 01 10 11 1 m4 y yz 01 F = B'D' + C'D' + A'BC F = F = Σ(0, 2, 4, 6, 7, 8, 10, 12) (a) AB CD C 00 m0 00 m4 m3 11 m5 m7 m13 m15 1 m9 m11 1 1 D F = C + D' F = (C'D)' 1 m6 1 1 m8 10 m2 1 1 m12 10 m1 11 1 01 A 01 1 m14 1 B D' C F m10 1 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 42 (b) AB CD C 00 01 m0 11 m1 00 1 m4 10 m3 m2 F = AD + B'D + CD F = ((AD)' (B'D)' (CD)')' 1 m5 m7 m6 01 A D 1 m12 m13 11 m15 1 A m8 m9 m11 10 B m14 B' D 1 1 m10 F C D 1 D (c) F = (A' + C' + D')(A' + C')(C' + D') F' = (A' + C' + D')' + (A' + C')' + (C' + D')' F' = ACD + AC + CD AB CD C 00 01 m0 00 m1 1 1 11 A (d) F 0 m11 1 B m14 0 m9 1 C 1 m15 1 m8 10 m6 0 m13 1 1 m7 1 m12 m2 0 m5 F = C' + A'D' F = (C(A + D))' F = (C(A'D')')' 10 m3 1 m4 01 11 A' D' m10 0 0 D AB CD C 00 m0 00 01 m12 m3 m13 m15 m9 1 m11 1 1 A m6 1 1 F = A' + B + D' F = (A(B')D)' 10 m2 1 m7 1 1 m8 11 1 m5 1 11 10 m1 1 m4 A 01 1 m14 B B' F 1 m10 D 1 D Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 43 3.17 AB CD C 00 m0 00 01 11 m1 1 10 m3 1 m2 1 m4 m5 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 01 1 11 A A' B' 1 B B' C F' 1 10 1 1 C D' D F = A'B' + B'C + CD' F = ((A + B)(B + C') (C' + D))' F = ((A'B')'(B'C)'(CD')' )' F' = (A'B')'(B'C)'(CD')' 3.18 F = (A ⊕ B)'(C ⊕ D) = (AB' + A'B)'(CD' + C'D) = (AB + A'B')(CD' + C'D) = ABCD' + ABC'D + A'B'CD' + A'B'C'D F' = (AB + A'B')' + (CD' + C'D)' F' = ( (A' + B')' + (A + B)' )' + ( (C' + D)' + (C + D')' )' AB CD C 00 m0 01 m1 00 11 m3 10 m2 1 A' B' 1 m4 m5 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 A B 01 11 A 1 1 10 B F' C' D C D' D Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 44 3.19 (a) F = (w + zʹ′)(xʹ′ + zʹ′)(wʹ′ + xʹ′ + yʹ′) yz wx y 00 00 01 11 w 10 m0 m4 1 1 m12 1 m8 1 01 11 10 m1 m3 m2 m5 m7 m6 m13 m15 m14 m9 1 m11 1 y z 1 x F w z m10 1 w x 1 z (b) wx F = y'z' + wx' + w'z' F =[(y + z)' + (w' + x)' + (w + z)'] F' =[(y + z)' + (w' + x)' + (w + z)']' yz y 00 m0 00 01 m1 11 m3 1 10 m2 y z' y' z 1 m4 m5 m7 m6 m12 m13 m15 m14 m9 m11 01 11 w 1 m8 x 1 m10 F' w x' w' x 10 z F = Σ(0, 3, 12, 15) F' =y'z+yz' + w'x + wx' = [(y + z')(w + x')(w + x')(w' + x)]' F = (y + z')' + (y' + z)' + (w + x')' + (w' + x)' (c) F = [(x + y)(x' + z)]' = (x + y)' + (x' + z)' F' = [(x + y)' + (x' + z)']' x y x' z F' Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 3.20 45 Multi-level NOR: F = ACD(B + C) + (BC' + DE') F' = [ACD(B + C) + (BC' + DE')]' F' = [(A' + C' + D')'(B + C) + (B' + C)' + (D' + E)']' F' = [((A' + C' + D') + (B + C)' )' + (B' + C)' + (D' + E)']' F' = [(A' + C' + D' + (B + C)')' + (B' + C)' + (D' + E)']' A' C' D' B C B' C F' D' E Multi-level NAND: F = CD(B + C)A + (BC' + DE') F' = [CD(B + C)A]' [BC' + DE']' F' = [CD(B'C')'A]' [BC' + DE']' F' = [CD(B'C')'A]' [[ (BC')' (DE')]' ]' B' C' A C D F B C' D E' 3.21 F = w(x + y + z) + xyz F' = [w(x + y + z)]'[xyz]' = [w(x'y'z')')]'(xyz)' x y z x' y' F z' w Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 46 3.22 z D C y B x w A z D C y B x w A Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 47 3.23 AB CD C 00 m0 00 01 m5 m12 11 10 m3 m2 m7 m6 m15 m14 x 1 11 1 A B' x m13 1 m8 10 m1 x m4 A 01 B C' D 1 m9 m11 F m10 x 1 D F = B'D' + AD' + C'D' F' = D + A'BC F = [D + A'BC]' = [D + (A + B' + C')']' 3.24 F(A, B, C, D) = S(0, 4, 8, 9, 10, 11, 12, 14) AB CD C 00 00 01 11 A 10 m0 01 11 10 m1 m3 m2 m5 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 m4 1 1 1 1 1 1 B 1 1 D (a) F = C'D' + AB' + AD' F' = (C'D')'(AB')'(AD')' AND-NAND: C' D' A B' F A D' (b) F' = [C'D' + AB' + AD']' AND-NOR: Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 48 C' D' F' A B' A D' (c) F = C'D' + AB' + AD' = (C + D)' + (A' + B)' + (A' + D)' F' = (C'D')'(AB')'(AD')' = (C + D)(A' + B)(A' + D) F = [ (C + D)(A' + B)(A' + D) ]' OR-NAND: C D F A' B A' D (d) F = C'D' + AB' + AD' = (C + D)' + (A' + B)' + (A' + D)' NOR-OR: C D F A' B A' D 3.25 A B A B ABCD C D A+B+C+D C D AND-AND AND OR-OR OR A B (AB CD)' C D A B (A + B + C + D)' C D AND-NAND NAND OR-NOR NOR A B (A'B'C'D')' C D A+B+C+D NOR-NAND OR A B [(AB)' + (C' D')]' C D NAND-NOR ABCD AND Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 49 A'B' A B A B A'B'C'D' C D NOR-AND A' + B' + C' + D' (A + B + C + D)' C D C'D' (A + B + C + D)' NOR NAND-OR NAND The degenerate forms use 2-input gates to implement the functionality of 4-input gates. 3.26 g = (a + b +c' + d')(b' + c' + d)(a'+ c + d') g' = a'b'cd + bcd' + ac'd cd c ab 00 01 11 10 f = abc' + c'd + a'cd'+ b'cd' ab cd c 00 00 01 11 a 10 01 m0 m1 m4 m5 m12 m8 1 11 10 m3 m2 m7 m6 m13 m15 m14 m9 m11 m10 1 1 1 1 1 00 1 01 b 11 a 1 10 m0 m4 1 1 m1 m5 1 1 m3 m7 0 1 m6 1 0 m12 m13 m15 m14 m8 m9 m11 m10 1 1 0 0 d 1 1 d b 0 1 fg = ac'd + abc'd + b'cd' 3.27 m2 x⊕ y = x'y + xy'; Dual = (x' + y)(x + y') = (x⊕ y)' 3.28 x y x y P z (a) 3-bit odd parity generator C z P (b) 4-bit odd parity generator Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 3.29 50 D=A⊕ B⊕C E = A'BC + AB'C = (A ⊕ B)C F = ABC' + (A' + B')C = ABC' + (AB)'C = (AB) ⊕ C G = ABC A B Half-Adder S C A B C Half-Adder Half-Adder AB 3.30 S D=A B C C E = (A B)C S F = (AB) C G = ABC C F = AB'CD' + A'BCD' + AB'C'D + A'BC'D F = (A ⊕ B)CD' + (A ⊕ B) C'D = (A ⊕ B)(C ⊕ D) A B F C D 3.31 Note: It is assumed that a complemented input is generated by another circuit that is not part of the circuit that is to be described. (a) module Fig_3_20a_gates (F, A, B, C, C_bar, D); output F; input A, B, C, C_bar, D; wire w1, w2, w3, w4; and (w1, C, D); or (w2, w1, B); and (w3, w2, A); and (w4, B, C_bar); or (F, w3, w4); endmodule (b) module Fig_3_20b_gates (F, A, B, B_Bar, C, C_bar, D); output F; input A, B, B_bar, C, C_bar, D; wire w1, w2, w3, w4; not (w1_bar, w1); not (w3_bar, w3); not (w4_bar, w4); nand (w1, C, D); or (w2, w1_bar, B); nand (w3, w2, A); nand (w4, B, C_bar); or (F, w3_bar, w4_bar); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 51 (c) module Fig_3_21a_gates (F, A, A_bar, B, B_bar, C, D_bar); output F; input A, A_bar, B, B_bar, C, D_bar; wire w1, w2, w3, w4; and (w1, A, B_bar); and (w2, A_bar, B); or (w3, w1, w2); or (w4, C, D_bar); and (F, w3, w4); endmodule (d) module Fig_3_21b_gates (F, A, A_bar, B, B_bar, C_bar, D); output F; input A, A_bar, B, B_bar, C_bar, D; wire w1, w2, w3, w4, F_bar; nand (w1, A, B_bar); nand (w2, A_bar, B); not (w1_bar, w1); not (w2_bar, w2); or (w3, w1_bar, w2_bar); or (w4, w5, w6); not (w5, C_bar); not (w6, D); nand (F_bar, w3, w4); not (F, F_bar); endmodule (e) module Fig_3_24_gates (F, A, A_bar, B, B_bar, C, D_bar); output F; input A, A_bar, B, B_bar, C, D_bar wire w1, w2, w3, w4, w5, w6, w7, w8, w7_bar, w8_bar; not (w1_bar, w1); not (w2_bar, w2); not (w3, E_bar); nor (w1, A, B); nor (W2, C, D); and (F, w1_bar, w2_bar, w3); endmodule (f) module Fig_3_25_gates (F, A, A_bar, B, B_bar, C, D_bar); output F; input A, A_bar, B, B_bar, C, D_bar; wire w1, w1_bar, w2, w2_bar; wire w3, w4, w5, w6, w7, w8; not (w1, A_bar); not (w2, B); not (w3, A); not (w4, B_bar); and (w5, w1_bar, w2_bar)); and (w6, w3, w4); nor (w7, w5, w6); nor (w8, c, d_bar); and (F, w7, w8); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 3.32 52 Note: It is assumed that a complemented input is generated by another circuit that is not part of the circuit that is to be described. Note: Because the signals here are all scalar–valued, the logical operators (!, &&, and ||) are equivalent to the bitwise operators (~, &, |). If the operands are vectors the bitwise operators produce a vector result; the logical operators would produce a sclara result (true or false). (a) module Fig_3_20a_CA (F, A, B, C, C_bar, D); output F; input A, B, C, C_bar, D; wire w1, w2, w3, w4; assign w1 = C && D; assign w2 = w1 || B; assign w3 = !(w2 && A); assign w4 = !w3; assign w5 = !(B && C_bar); assign w5_bar = !w5; assign F = w4 || w5_bar); endmodule (b) module Fig_3_20b_CA (F, A, B, C, C_bar, D); output F; input A, B, B_bar, C, C_bar, D; wire w2 = !w1; wire w3 = !B_bar; wire w4, w5, w5_bar, w6, w6_bar; assign w1 = !(C && D); assign w4 = w2 || w3; assign w5 = !(w4 && A); assign w5_bar = !w5; assign w6 = !(B && C_bar); assign w6_bar = !w6; assign F = w5_bar || w6_bar; endmodule module Fig_3_21a_CA (F, A, A_bar, B, B_bar, C, D_bar); output F; input A, A_bar, B, B_bar, C, D_bar; wire w1, w2, w3, w4; assign w1 = A && B_bar; assign w2 = A_bar && B; assign w3 = w1 || w2); assign w4 = C || D_bar; assign F = w3 || w4; endmodule (c) (d) module Fig_3_21b_CA (F, A, A_bar, B, B_bar, C_bar, D); output F; input A, A_bar, B, B_bar, C_bar, D; wire w1, w2, w1_bar, w2_bar, w3, w4, w5, w6, F_bar; assign w1 = !(A && B_bar); assign w2 = !(A_bar && B); assign w1_bar = !w1; assign w2_bar = !w2; assign w3 = w1_bar || w2_bar; assign w4 = !C_bar; assign w5 = !D; assign w6 = w4 || w5; assign F_bar = !(w3 && w6); assign F = !F_bar; endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 3.33 53 (e) module Fig_3_24_CA (F, A, B, C, D, E_bar); output F; input A, B, C, D, E_bar; wire w1, w2, w1_bar, w2_bar, w3_bar; assign w1 = !(A || B); assign w1_bar = !w1; assign w2 = !(C || D); assign w2_bar = !w2; assign w3 = !E_bar; assign F = w1_bar && w2_bar && w3; endmodule (f) module Fig_3_25_CA (F, A, A_bar, B, B_bar, C, D_bar); output F; input A, A_bar, B, B_bar, C, D_bar wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10; assign w1 = !A _bar; assign w2 = !B; assign w3 = w1 && w2; assign w4 = !A; assign w5 = !B_bar; assign w6 = w4 && w5; assign w7 = !(C || D_bar); assign w8 = !(w3 || w6); assign w9 = !w8; assign w10 = !w7; assign F = w9 && w10; endmodule (a) Initially, with xy = 00, w1 = w2 = 1, w3 = w4 = 0 and F = 0. w1 should change to 0 3ns after xy changes to 01. w4 should change to 1 6ns after xy changes to 01. F should change from 0 to 1 8ns after w4 changes from 0 to 1, i.e., 14 ns after xy changes from 00 to 01. w3 x w1 6 F=x y 3 3 8 w2 y 6 w4 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 54 (b) `timescale 1ns/1ps module Prob_3_33 (F, x, y); wire w1, w2, w3, w4; and #6 (w3, x, w1); not #3 (w1, x); and #6 (w4, y, w1); not #3 (w2, y); or #8 (F, w3, w4); endmodule module t_Prob_3_33 (); reg x, y; wire F; Prob_3_33 M0 (F, x, y); initial #200 $finish; initial fork x = 0; y = 0; #20 y = 1; join endmodule (c) To simulate the circuit, it is assumed that the inputs xy = 00 have been applied sufficiently long for the circuit to be stable before xy = 01 is applied. The testbench sets xy = 00 at t = 0 ns, and xy = 1 at t = 10 ns. The simulator assumes that xy = 00 has been applied long enough for the circuit to be in a stable state at t = 0 ns, and shows F = 0 as the value of the output at t = 0. For illustration, the waveforms show the response to xy = 01 applied at t = 10 ns. Name x w1 y w2 w3 w4 F t = 10 ns t = 24 ns Note: input change occurs at t = 10 ns. t = 16 ns Δ = 14 ns Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 55 3.34 module Prob_3_34 (Out_1, Out_2, Out_3, A, B, C, D); output Out_1, Out_2, Out_3; input A, B, C, D; wire A_bar, B_bar, C_bar, D_bar; assign A_bar = !A; assign B_Bar = !B; assign C_bar = !C; assign D_bar = !D; assign Out_1 = (A + B_bar) && C_bar && ( C || D); assign Out_2 = ( (C_bar && D) || (B && C && D) || (C && D_bar) ) && (A_bar || B); assign Out_3 = (((A && B) || C) && D) || (B_bar && C); endmodule 3.35 module Exmpl-3(A, B, C, D, F) inputs A, B, C, Output D, F, output B and g1(A, B, B); not (D, B, A), OR (F, B; C); endofmodule; // Line 1 // Line 2 // Line 3 // Line 4 // Line 5 // Line 6 // Line 7 Line 1: Dash not allowed character in identifier; use underscore: Exmpl_3. Terminate line with semicolon (;). Line 2: inputs should be input (no s at the end). Change last comma (,) to semicolon (;). Output is declared but does not appear in the port list, and should be followed by a comma if it is intended to be in the list of inputs. If Output is a mispelling of output and is to declare output ports, C should be followed by a semicolon (;) and F should be followed by a semicolon (;). Line 3: B cannot be declared both as an input (Line 2) and output (Line 3). Terminate the line with a semicolon (;). Line 4: A cannot be an output of the primitive if it is an input to the module Line 5: Too many entries for the not gate (may have only a single input, and a single output). Termiante the line with a semicolon, not a comma. Line 6: OR must be in lowercase: change to "or". Replace semicolon by a comma (B,) in the list of ports. Line 7: Remove semicolon (no semicolon after endmodule). Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 3.36 56 (a) B C D x d z a A w F y (b) A1 A0 B1 B0 w1 w6 w2 w7 w3 w4 F1 F2 F3 w5 (c) a b y1 y2 y3 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 57 3.37 UDP_Majority_4 (y, a, b, c, d); output y; input a, b, c, d; table // a b c d : y 0 0 0 0 : 0; 0 0 0 1 : 0; 0 0 1 0 : 0; 0 0 1 1 : 0; 0 1 0 0 : 0; 0 1 0 1 : 0; 0 1 1 0 : 0; 0 1 1 1 : 1; 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 endtable endprimitive : : : : : : : : 0; 0; 0; 0; 0; 0; 1; 1; 3.38 module t_Circuit_with_UDP_02467; wire E, F; reg A, B, C, D; Circuit_with_UDP_02467 m0 (E, F, A, B, C, D); initial #100 $finish; initial fork A = 0; B = 0; C = 0; D = 0; #40 A = 1; #20 B = 1; #40 B = 0; #60 B = 1; #10 C = 1; #20 C = 0; #30 C = 1; #40 C = 0; #50 C = 1; #60 C = 0; #70 C = 1; #20 D = 1; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 58 // Verilog model: User-defined Primitive primitive UDP_02467 (D, A, B, C); output D; input A, B, C; // Truth table for D = f (A, B, C) = S (0, 2, 4, 6, 7); table // A B C : D // Column header comment 0 0 0 : 1; 0 0 1 : 0; 0 1 0 : 1; 0 1 1 : 0; 1 0 0 : 1; 1 0 1 : 0; 1 1 0 : 1; 1 1 1 : 1; endtable endprimitive // Verilog model: Circuit instantiation of Circuit_UDP_02467 module Circuit_with_UDP_02467 (e, f, a, b, c, d); output e, f; input a, b, c, d; UDP_02467 M0 (e, a, b, c); and (f, e, d); //Option gate instance name omitted endmodule A 10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80 t, ns B t, ns C t, ns D t, ns E t, ns F t, ns Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 59 3.39 a 0 0 1 1 b 0 1 0 1 s 0 1 1 0 c 0 0 0 1 s = a'b + ab' = a ^ b c = ab = a && b module Prob_3_39 (s, c, a, b); input a, b; output s, c; xor (s, a, b); and (c, a, b); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 60 CHAPTER 4 4.1 (a) T1 = B'C, T2 = A'B, T3 = A + T1 = A + B'C, T4 = D ⊕ T2 = D ⊕ (A'B) = A'BD' + D(A + B') = A'BD' + AD + B'D F1 = T3 + T4 = A + B'C + A'BD' + AD + B'D With A + AD = A and A + A'BD' = A + BD': F1 = A + B'C + BD' + B'D Alternative cover: F1 = A + CD' + BD' + B'D F2 = T2 + D' = A'B + D' AB ABCD T1 T2 T3 T4 F1 F2 0000 0001 0010 0011 0100 0101 0110 0111 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0 1 0 1 1 0 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1000 1001 1010 1011 1100 1101 1110 1111 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 CD M0 00 11 M1 M3 M2 M5 M7 M6 01 M0 11 1 M13 1 M15 M4 1 M8 1 M9 M11 1 11 D F2 = A'B + D' M2 1 1 M5 M7 M6 M13 M15 M14 1 1 A 1 M8 10 M9 1 1 M11 1 B 1 M10 1 1 D F1 = A + B'C+ B'D + BD' AB CD C 00 01 M4 M5 M7 M6 M13 M15 M14 1 11 1 1 1 1 M8 10 M2 1 1 M12 A M3 10 M1 01 B 11 M0 00 M10 1 10 M3 1 M12 1 M14 M1 11 1 01 1 1 M12 01 00 10 1 M4 10 01 C 00 C 00 A CD M9 1 1 M11 1 1 B 1 M10 1 D F1 = A + CD' + B'D + BD' Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 61 4.2 [(A'D)' A']'= A + D A' A F B C BC + A' BC G D (A'D)' = A + D' F = (A + D)(A' + BC) = A'D + ABC + BCD += A'D + ABC F = (A + D')(A' +BC) = A'D' + ABC + BCD' = A'D' + ABC AB CD C 00 00 01 11 A 10 01 m0 m1 m4 m5 11 m3 1 m7 1 AB 10 m2 1 01 m12 m13 m15 m14 m8 m9 m11 m10 1 B 1 C 00 00 m6 1 CD 11 A 10 m0 11 10 m1 m3 m2 m5 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 m4 D 1 1 1 1 1 B 1 D G = A'D' + ABC + BCD' = A'D' + ABC F = A'D + ABC + BCD = A'D + ABC 4.3 01 (a) Yi = (AiS' + BiS)E' for i = 0, 1, 2, 3 (b) 1024 rows and 14 columns 4.4 (a) xyz F 000 001 010 011 100 101 110 111 1 1 1 0 0 0 0 0 x 00 0 x y yz 1 m0 m4 1 01 m1 11 1 m5 10 m3 m2 m7 m6 1 x' y' F x' y' z F = x'y' + x'z' Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 62 (b) xyz F 000 001 010 011 100 101 110 111 0 1 0 0 0 0 0 0 x 00 0 x y yz 1 01 m0 m1 m4 m5 11 m3 1 1 m7 1 10 m2 z F m6 1 z F=z 4.5 xyz ABC 000 001 010 011 100 101 110 111 010 011 100 101 001 010 011 100 x 00 0 x A yz 1 y 01 11 m0 m1 m3 m4 m5 m7 10 m2 1 x' y 1 A m6 1 y z z A = x'y + yz x 00 0 x B yz 1 m0 1 m4 y 01 m1 m5 11 1 1 10 m3 m2 m7 m6 y 00 0 x 1 z' C 01 m0 m1 m4 m5 1 1 B x B = x'y' + y'z + xyz' x y' z 1 z yz x y' y 11 m3 1 m7 10 m2 m6 1 x z C z C= x'z + xz' Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 63 4.6 xyz F 000 001 010 011 100 101 110 111 0 0 0 1 0 1 1 1 x 00 0 x A yz 1 01 m0 m1 m4 m5 1 y 11 m3 m7 1 1 10 m2 m6 z F = xz + yz + xy 1 x z y z x y F module Prob_4_6 (output F, input x, y, z); assign F = (x & z) | (y & z) | (x & y); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 64 4.7 (a) ABCD 0000 0001 0011 0010 0110 0111 0101 0100 wxyz 1100 1101 1111 1110 1010 1011 1001 1000 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 AB CD C 00 00 01 11 A 10 01 11 CD 10 m0 m1 m3 m2 m4 m5 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 1 1 00 01 B 1 1 11 A 1 10 D CD C 00 00 01 11 A 10 01 11 m1 m3 m4 m5 m7 m6 1 1 m2 1 m13 m15 m14 m8 m9 m11 m10 1 1 m4 1 m1 m5 1 11 10 m3 m7 m2 m6 1 1 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 CD B 1 00 B 1 11 A 10 D y = A'B'C A'BC' + ABC + AB'C' = A'(A B) + A(B C)' =A B C = X C C 00 01 m12 1 AB 10 m0 1 m0 01 D x = AB' + A'B = A B w=A AB C 00 01 m0 m1 m4 w B x C y 10 m3 m2 m5 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 1 z=A B =y D A 11 1 B 1 1 D C 1 D z D Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 65 (b) module Prob_4_7(output w, x, y, z, input A, B, C, D); always @ (A, B, C, D) case ({A, B, C, D}) 4'b0000: {w, x, y, z} = 4'b0000; 4'b0001: {w, x, y, z} = 4'b1111; 4'b0010: {w, x, y, z} = 4'b1110; 4'b0011: {w, x, y, z} = 4'b1101; 4'b0100: {w, x, y, z} = 4'b1100; 4'b0101: {w, x, y, z} = 4'b1011; 4'b0110: {w, x, y, z} = 4'b1010; 4'b0111: {w, x, y, z} = 4'b1001; 4'b1000: 4'b1001: 4'b1010: 4'b1011: 4'b1100: 4'b1101: 4'b1110: 4'b1111: endcase endmodule {w, x, y, z} = 4'b1000; {w, x, y, z} = 4'b0111; {w, x, y, z} = 4'b0110; {w, x, y, z} = 4'b0101; {w, x, y, z} = 4'b0100; {w, x, y, z} = 4'b0011; {w, x, y, z} = 4'b0010; {w, x, y, z} = 4'b0001; Alternative model: module Prob_4_7(output w, x, y, z, input A, B, C, D); assign w = A; assign x = A ^ B); assign y = x ^ C; assign z = y ^ D; endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 4.8 66 (a) The 8-4-2-1 code (Table 1.5) and the BCD code (Table 1.4) are identical for digits 0 – 9. (b) 8421 Gray ABCD wxyz 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 AB CD C 00 01 11 CD 10 m0 m1 m3 m2 m4 m5 m7 m6 m0 00 m4 01 m12 m13 m15 m14 B 11 m8 m5 10 m3 m2 m7 1 1 m6 1 1 m12 m13 m15 m14 m9 m11 1 A m10 1 m8 m9 m11 m10 10 1 D w = AB'C' CD B 01 11 m1 m3 m4 m5 m7 m6 m15 m14 1 m12 1 C 00 01 m0 m1 m4 m5 m12 m13 00 1 m13 CD m2 1 01 AB 10 m0 00 1 D x = AB'C' + A'B C 00 m9 m11 m10 10 A 10 m3 m2 m7 m6 m15 m14 m11 m10 1 1 11 m8 11 1 01 B 11 A m1 11 11 10 AB 01 00 01 A C 00 1 B 1 m8 m9 10 D y = A'BD' + A'B'D D z = A'C'D + BC'D + A'CD' Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 67 4.9 ABCD a b c 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 d e f g 1 0 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 1 1 1 0 0 0 1 1 1 0 1 1 AB CD C 00 m0 00 01 11 A 10 01 11 m1 m3 m4 m5 m7 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 1 m2 1 m6 1 CD AB 10 1 00 1 C 00 01 B 11 A 10 m0 m4 1 01 m1 1 11 m3 10 m2 1 1 m5 m7 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 D m6 1 B D a = A'C + A'BD + B'C'D' + AB'C' b = A'B' + A'C'D' + A'CD + AB'C' AB CD C 00 00 01 11 A 10 m0 m4 01 m1 1 m5 1 11 m3 1 m7 1 1 1 m2 m6 1 m13 m15 m14 m8 m9 m11 m10 1 C 00 00 m12 1 CD AB 10 01 B 11 A 10 m0 01 11 10 m1 m3 m4 m5 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 1 D m2 1 1 1 B D c = A'B + A'D + B'C'D' + AB'C' d = A'CD' + A'B' C+ B'C'D' + AB'C' + A'BC'D AB CD C 00 00 01 11 A 10 m0 01 11 m3 m2 m4 m5 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 1 1 D e = A'CD' + B'C'D' AB 10 m1 1 CD 00 00 1 C 01 B 11 A 10 m0 m4 1 1 01 11 m3 m2 m5 m7 m6 1 1 m13 m15 m14 m8 m9 m11 m10 1 D f = A'BC' + A'C'D' + A'BD + AB'C' C 00 00 m12 1 AB 10 m1 CD 01 B 11 A 10 01 11 10 m0 m1 m3 m4 m5 m7 m6 1 1 1 m2 1 1 m12 m13 m15 m14 m8 m9 m11 m10 1 1 D g = A'CD' + A'B'C + A'BC' + AB'C' Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. B 68 4.10 ABCD wxyz 0000 0000 0001 1111 0010 1110 0011 1101 0100 1100 0101 1011 0110 1001 0111 1000 1000 1001 1010 1011 1100 1101 1110 1111 1000 0111 0110 0101 0100 0011 0010 0001 AB CD C 00 00 01 11 A 10 01 m0 m1 m4 m5 1 1 1 11 m3 m7 CD 10 m2 1 m6 1 1 m13 m15 m14 m8 m9 m11 m10 1 00 1 m12 01 B 11 A 10 D w = A'(B + C + D) + AB'C'D' = A (B + C + D) AB CD 00 01 11 A 10 01 m0 m1 m4 m5 m12 m8 11 m2 m7 m6 m13 m15 m14 m9 m11 m10 1 1 1 AB 10 m3 1 11 m1 m4 m5 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 1 m3 10 m0 m2 1 1 1 1 B 1 01 B 1 C 00 00 1 1 CD 11 A 10 01 11 m1 m4 m5 m12 m13 m15 m14 m8 m9 m11 m10 y = CD' + C'D = C D For a 5-bit 2's complementer with input E and output v: 1 1 1 1 m3 10 m0 D v=E 01 D x = B'(C + D) + CB'D' = B (C + D) C 00 C 00 m7 1 1 1 1 m2 m6 B D z=D (A + B + C + D) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 69 4.11 (a) A3 A2 A1 A0 1 x x y Half Adder Half Adder S C x y Half Adder S C x y Half Adder S C y S C Note: 5-bit output (b) A3 x 1 A2 B x y Full Adder D 1 A1 x y Full Adder y Full Adder D B 1 D B A0 1 x y Half Adder B D Note: To decrement the 4-bit number, add -1 to the number. In 2's complement format ( add Fh ) to the number. An attempt to decrement 0 will assert the borrow bit. For waveforms, see solution to Problem 4.52. 4.12 (a) x 0 0 1 1 y 0 1 0 1 B 0 1 0 0 D 0 1 1 0 (b) x y Bin 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 B 0 1 1 1 0 0 0 1 D 0 1 1 0 1 0 0 1 D = x'y + xy' B = x'y Diff = x y z Bout = x'y + x'z + yz Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 70 4.13 4.14 Sum C V (a) 1101 0 1 (b) 0001 1 1 (c) 0100 1 0 (d) 1011 0 1 (e) 1111 0 0 xor AND OR 10 4.15 + 5 + 5 XOR + 10 = 30 ns C4 = G3 + P3C3 = G3 + P3(G2 + P2G1 + P2P1G0 + P2P1P0C0) = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0 4.16 (a) (C'G'i + p'i)' = (Ci + Gi)Pi = GiPi + PiCi = AiBi(Ai + Bi) + PiCi = A iB i + P iC i = G i + P iC i = AiBi + (Ai + Bi)Ci = AiBi + AiCi + BiCi = Ci+1 (PiG'i) ⊕ Ci = (Ai + Bi)(AiBi)' ⊕ Ci = (Ai + Bi)(A'i + B'i) ⊕ Ci = (A'iBi + AiB'i) ⊕ Ci = Ai ⊕ Bi ⊕ Ci = Si (b) Output of NOR gate = (A0 + B0)' = P'0 Output of NAND gate = (A0B0)' = G'0 S1 = (P0G'0) ⊕ C0 C1 = (C'0G'0 + P'0)' as defined in part (a) 4.17 (a) (C'iG'i + P'i)' = (Ci + Gi)Pi = GiPi + PiCi = AiBi(Ai + Bi) + PiCi = A iB i + P iC i = G i + P iC i = AiBi + (Ai + Bi)Ci = AiBi + AiCi + BiCi = Ci+1 (PiG'i)⊕Ci = (Ai + Bi)(AiBi)'⊕Ci = (Ai + Bi)(A'i + B'i)⊕Ci = (A'iBi + AiB'i)⊕Ci = Ai⊕Bi⊕Ci = Si (b) Output of NOR gate = (A0 + B0)' = P'0 Output of NAND gate = (A0B0)' = G'0 S0 = (P0G'0)⊕C0 C1 = (C'0G'0 + P'0)' as defined in part (a) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 71 4.18 Inputs Outputs ABCD wxyz 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 AB 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 CD C 00 00 01 11 A 10 m0 1 m4 11 10 m1 1 11 m3 m2 m7 m6 00 01 m13 m15 m14 m8 m9 m11 m10 x x x x D w = A'B'C' C 01 11 10 1 00 1 01 m5 m7 m12 m13 m15 m14 m8 m9 m11 m10 x x 10 CD AB m4 x A m2 m6 B x 11 A x 10 D y=C m0 m4 1 01 m1 m5 1 11 m3 10 m2 1 m7 1 m6 m12 m13 m15 m14 m8 m9 m11 m10 x x x B x x x C C 00 m0 m4 1 1 01 m1 m5 1 11 10 m3 m2 m7 m6 1 1 m12 m13 m15 m14 m8 m9 m11 m10 x 1 x x x D z = D' C 00 D x = BC' + B'C = B m3 x 11 x m1 1 B x m0 1 CD AB 10 m12 00 01 01 m5 CD 00 d(A, b, c, d) = Σ(10, 11, 12, 13, 14, 15) B x x Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 72 4.19 Mode = 0 FOR Add Mode = 1 for Subtract B3 B2 B1 B0 9's Complementer (See Problem 4.18) Select = 1 Select Select = 0 Quadruple 2 x 1 MUX A3 A2 A1 A0 Cin BCD Adder (See Fig. 4.14) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 4.20 73 Combine the following circuit with the 4-bit binary multiplier circuit of Fig. 4.16. C6 A3 B3 B2 Cout D7 B1 C2 C1 C0 B0 4-bit Adder D6 C5 C4 C3 D5 Augend D4 D3 D2 D1 D0 4.21 A0 B0 A1 B1 A2 B2 x A3 B3 x = (A0 B0)'(A1 B1)'(A2 B2)'(A3 B3)' 4.22 XS-3 Binary ABCD wxyz 0011 0000 0100 0001 0101 0010 0110 0011 0111 0100 1000 0101 1001 0110 1010 0111 1011 1000 1100 1001 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 74 AB CD C 00 00 01 11 A 10 m0 x m4 01 m1 x m5 11 m3 x m7 m6 00 01 m12 m13 m15 m14 m8 m9 m11 m10 1 x CD AB 10 x 1 B x 11 A 10 D w = AB + ACD C 00 m0 X 01 m1 X 11 m3 m7 10 m2 m4 m5 m12 m13 m15 m14 m8 m9 m11 m10 x 1 1 1 x m6 x (NOR) (NOR) (NOR) (NOR) A1 A0 D0' = (A1'A0')' D1' = (A1'A0)' D2' = (A1A0')' D0' = (A1A0)' (NAND) (NAND) (NAND) (NAND) D0 = (A1 + A0 + E' )' = A'1A'0E D1 = (A1 + A'0 + E' )' = A'1A0E D2 = (A'1 + A0 + E' ) = A1A'0E D3 = (A'1 + A'0 + E' )' = A1A0E E E A1 1 D x = B'C' + B'D' + BCD y = C'D + CD' z = D' 4.23 D0 = A1'A0' = (A1 + A0)' D1 = A1'A0 = (A1 + A0')' D2 = A1A0' = (A1' + A0)' D3 = A1A0 = (A1' + A0)' X A0 D0' = (A1 + A0 + E' ) = (A'1A'0E)' D0 D1' = (A1 + A'0 + E' ) = (A'1A0E)' D1 D2' = (A1' + A0 + E' ) = (A1A0'E)' D2 D3' = (A1' + A0' + E' ) = (A1A0E)' D3 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. B 75 4.24 AB CD C 00 m0 Inputs: A, B, C, D D0 = A'B'C'D' D1 = A'B'C'D D2 = B'CD' D3 = B'CD D4 = BC'D' 00 Outputs: D0, D1, ... D9 D5 = BC'D D6 = BCD' D7 = BCD D8 = AD' A D9 = AD D0 m4 01 D4 D8 11 m3 D1 D3 m7 D5 m13 x m8 10 m1 m5 m12 11 01 m9 D9 10 D2 m6 D7 m15 x x x m11 x D6 m14 B x m10 x D Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 76 4.25 A0 A1 A2 3x8 Decoder 8 D0 - D7 E 3x8 Decoder 8 D8 - D15 E A3 0 20 2x4 Decoder A4 21 E 1 2 3 3x8 Decoder 8 3x8 Decoder 8 2x4 Decoder 4 D16 - D23 E E D24 - D31 E 4.26 A0 20 A1 1 2 20 1 2 A2 2x4 Decoder 4 D4 - D7 E 0 20 2x4 Decoder A3 D0 - D3 E 21 E 1 2 20 3 1 2 2x4 Decoder 4 2x4 Decoder 4 D8 - D11 E E 20 1 2 D12 - D15 E Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 77 4.27 F1 = Σ(1, 4, 6) 0 1 2 2 3x8 2 3 21 Decoder 4 0 2 5 6 7 A B C F2 = Σ(3, 5) F3 = Σ(2, 4, 6, 7) 4.28 (a) F1 = x(y + y')z + x'yz' =xyx + xy'z + x'yz' = Σ(2, 5, 7) F2 = xy'z' + x'y = xy'z' + x'yz + x'yz' = Σ(2, 3, 4) F3 = x'y'z' + xy(z + z') =x'y'z' + xyz + xyz' = Σ(0, 6, 7) 0 1 x y z 22 3 x 8 2 21 Decoder 3 4 20 5 6 7 F1 = Σ((2, 5, 7) F1 = Σ((2, 3, 4) F1 = Σ(0, 6, 7) (b) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 78 4.29 D1D0 D3D2 00 Inputs D3 D2 D1 D0 Outputs x y V 0 0 0 0 x x x 1 x x 1 0 x 1 0 0 1 0 0 0 x 0 0 1 1 x 0 1 0 1 D1 01 m0 m1 m4 m5 00 1 01 0 1 1 1 1 1 m12 11 D3 11 m3 1 1 m8 10 1 m9 m6 1 1 m15 1 1 1 m7 m13 10 m2 m14 1 m11 1 D2 1 m10 1 1 D0 V = D0 + D1 + D2 + D3 D3D2 D1D0 00 m0 00 11 10 m1 m3 m2 m5 m7 m6 m13 m15 m14 m9 m11 m10 D3D2 x m4 01 11 m0 D1 01 11 10 m1 m3 m2 m4 m5 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 x 1 01 D2 1 m8 D1D0 00 00 1 m12 10 01 1 11 D3 1 10 D2 1 1 1 D0 D0 x = D1'D0' y = D0'D2' + D1D0' D0 x D1 y D2 D2 D3 D1 D0 V Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 79 4.30 Inputs Outputs D0 D1 D2 D3 D4 D5 D6 D7 x y z V 0 1 x x x x x x x x 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 x x x x x x 0 0 0 1 x x x x x 0 0 0 0 1 x x x x 0 0 0 0 0 1 x x x 0 0 0 0 0 0 1 x x 0 0 0 0 0 0 0 1 x 0 0 0 0 0 0 0 0 1 If D2 = 1, D6 = 1, all others = 0 Output xyz = 100 and V = 1 4.31 s0 s1 s2 s3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s0 s1 s2 0 1 2 3 4 5 6 7 s0 s1 s2 0 1 2 3 4 5 6 7 x 0 0 1 1 0 0 0 1 x 0 1 0 1 0 1 0 1 8x1 MUX s 0 1 2x1 MUX y 8x1 MUX Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. (a) F = Σ (0, 2, 5, 8, 10, 14) Inputs ABCD 000 0 000 1 001 0 001 1 010 0 010 1 011 0 011 1 100 0 100 1 101 0 101 1 110 0 110 1 111 0 111 1 Mux input line (ABC) Value 4.32 80 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 F = Σ(0, 2, 5, 8, 10, 14) 1 F = D' 0 1 F = D' 0 0 F=D 1 0F=0 0 1 F = D' 0 1 F = D' 0 0F=0 0 1 F = D' 0 A B C D 0 s0 s1 s2 0 1 2 3 4 5 6 7 8x1 MUX Y Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. F 81 Inputs ABCD 000 0 000 1 001 0 001 1 010 0 010 1 011 0 011 1 100 0 100 1 101 0 101 1 110 0 110 1 111 0 111 1 Mux input line (ABC) Value (b) F = Π(2, 6, 11) = (A' +B' + C + D')(A' +B + C + D')(A +B' + C + D) F' = (A' +B' + C + D')' + (A' +B + C + D')' + (A +B' + C + D)' F' = (ABC'D) + (AB'C'D) + (A'BC'D') = Σ(13, 9, 4) F = Σ(0, 1, 2, 3, 5, 6, 7, 8, 10, 11, 12, 14, 15) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 1F = 1 1 1 F=1 1 0 F=D 1 1F = 1 1 1 F = D' 0 1 F=1 1 1F = D' 0 1 F=1 1 s0 s1 s2 0 1 2 3 4 5 6 7 A B C D 1 8x1 MUX F Y 4.33 S(x, y, z) = Σ(1, 2, 4, 7) C(x, y, z) = Σ(3, 5, 6, 7) S I0 I1 I2 I3 x' 0 1 2 3 4 5 6 7 x x' x' x x C x' x 0 1 2 3 x Dual 4x1 MUX I0 I1 I2 I3 0 1 2 3 4 5 6 7 0 x' x' 1 0 1 S 0 1 2 3 Y C y z Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 82 4.34 (a) A B C D F AB 0 0 1 I5 = 1 1 0 I0 = D 0 1 I4 = D 1 1 I6 = D' 1 1 1 0 0 0 0 0 0 1 1 I3 = 1 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 1 0 1 1 0 C 00 00 01 11 A 10 01 11 10 m0 m1 m4 m5 m7 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 m3 m2 m6 1 1 1 B 1 D Other minterms = 0 since I1 = I2 = I7 = 0 CD F(A, B, C, D) = Σ(1, 6, 7, 9, 10, 11, 12) (b) A B 0 0 I2 = 0 0 0 0 I3 = 1 0 1 I7 = 1 1 I4 = D 1 1 0 I0 = D' 0 1 I6= D' 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 I1 = 0 C 1 1 0 0 1 1 1 1 0 0 0 0 0 0 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 0 0 0 0 1 1 1 1 0 1 1 0 1 0 AB CD C 00 00 01 11 A 10 m0 1 01 m1 1 11 m3 10 m2 m4 m5 m7 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 1 m6 1 B 1 D F(A, B, C, D) = Σ(0, 1, 6, 7, 9, 13, 14, 15) Other minterms = 0 since I1 = I2 = 0 4.35 (a) Inputs ABCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 F 0 1 0 1 1 0 0 0 0 0 0 1 1 1 1 1 AB = 00 F=D A B AB = 01 F = C'D' = (C + D)' C D AB = 10 F = CD s0 s1 0 1 2 3 4x1 MUX Y F 1 AB = 11 F=1 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 83 (b) F = S(1, 2, 5, 7, 8, 10, 11, 13, 15) Inputs ABCD F2 = Σ(1, 2, 5, 7, 8, 10, 11, 13, 15) A 0000 0 0001 1 AB = 00 B 0010 1 F = C'D + CD' 0011 0 C 0100 0 AB = 01 0101 1 F = C'D + CD = D 0110 0 D 0111 1 1000 1 1001 0 1010 1 AB = 10 1011 1 F = C'D' + C'D + CD = C'D' + D 1100 0 AB = 11 1101 1 F=D 1110 0 1111 1 4.36 4.37 s0 s1 0 1 4x1 MUX Y F2 2 3 module priority_encoder_gates (output x, y, V, input D0, D1, D2, D3); // V2001 wire w1, D2_not; not (D2_not, D2); or (x, D2, D3); or (V, D0, D1, x); and (w1, D2_not, D1); or (y, D3, w1); endmodule Note: See Problem 4.45 for testbench) module Add_Sub_4_bit ( output [3: 0] S, output C, input [3: 0] A, B, input M ); wire [3: 0] B_xor_M; wire C1, C2, C3, C4; assign C = C4; // output carry xor (B_xor_M[0], B[0], M); xor (B_xor_M[1], B[1], M); xor (B_xor_M[2], B[2], M); xor (B_xor_M[3], B[3], M); // Instantiate full adders full_adder FA0 (S[0], C1, A[0], B_xor_M[0], M); full_adder FA1 (S[1], C2, A[1], B_xor_M[1], C1); full_adder FA2 (S[2], C3, A[2], B_xor_M[2], C2); full_adder FA3 (S[3], C4, A[3], B_xor_M[3], C3); endmodule module full_adder (output S, C, input x, y, z); // See HDL Example 4.2 wire S1, C1, C2; // instantiate half adders half_adder HA1 (S1, C1, x, y); half_adder HA2 (S, C2, S1, z); or G1 (C, C2, C1); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 84 module half_adder (output S, C, input x, y); xor (S, x, y); and (C, x, y); endmodule // See HDL Example 4.2 module t_Add_Sub_4_bit (); wire [3: 0] S; wire C; reg [3: 0] A, B; reg M; Add_Sub_4_bit M0 (S, C, A, B, M); initial #100 $finish; initial fork #10 M = 0; #10 A = 4'hA; #10 B = 4'h5; #50 M = 1; #70 B = 4'h3; join endmodule Name 0 50 A[3:0] x B[3:0] x 100 a 5 3 M S[3:0] x f 5 7 C 4.38 module quad_2x1_mux ( // V2001 input [3: 0] A, B, // 4-bit data channels input enable_bar, select, // enable_bar is active-low) output [3: 0] Y // 4-bit mux output ); //assign Y = enable_bar ? 0 : (select ? B : A); // Grounds output assign Y = enable_bar ? 4'bzzzz : (select ? B : A); // Three-state output endmodule // Note that this mux grounds the output when the mux is not active. module t_quad_2x1_mux (); reg [3: 0] A, B, C; reg enable_bar, select; wire [3: 0] Y; // 4-bit data channels // enable_bar is active-low) // 4-bit mux quad_2x1_mux M0 (A, B, enable_bar, select, Y); initial #200 $finish; initial fork enable_bar = 1; select = 1; A = 4'hA; B = 4'h5; #10 select = 0; // channel A Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 85 #20 enable_bar = 0; #30 A = 4'h0; #40 A = 4'hF; #50 enable_bar = 1; #60 select = 1; // channel B #70 enable_bar = 0; #80 B = 4'h00; #90 B = 4'hA; #100 B = 4'hF; #110 enable_bar = 1; #120 select = 0; #130 select = 1; #140 enable_bar = 1; join endmodule Name 0 70 a A[3:0] 140 0 f 5 B[3:0] 0 a 0 a f enable_bar select Y[3:0] 0 a 0 f 0 5 f 0 With three-state output: Name 0 70 a A[3:0] 140 0 f 5 B[3:0] 0 a 0 a f enable_bar select Y[3:0] 4.39 z a 0 f z 5 f z // Verilog 1995 module Compare (A, B, Y); input [3: 0] A, B; // 4-bit data inputs. output [5: 0] Y; // 6-bit comparator output. reg [5: 0] Y; // EQ, NE, GT, LT, GE, LE always @ (A or B) if (A==B) Y = 6'b10_0011; else if (A < B) Y = 6'b01_0101; else Y = 6'b01_1010; endmodule // EQ, GE, LE // NE, LT, LE // NE, GT, GE // Verilog 2001, 2005 module Compare (input [3: 0] A, B, output reg [5:0] Y); always @ (A, B) if (A==B) Y = 6'b10_0011; // EQ, GE, LE else if (A < B) Y = 6'b01_0101; // NE, LT, LE else Y = 6'b01_1010; // NE, GT, GE endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 86 4.40 module Prob_4_40 ( output [3: 0] sum_diff, output carry_borrow, input [3: 0] A, B, input sel_diff ); always @(sel_diff, A, B) endmodule {carry_borrow, sum_diff} = sel_diff ? A - B : A + B; module t_Prob_4_40; wire [3: 0] sum_diff; wire carry_borrow; reg [3:0] A, B; reg sel_diff; integer I, J, K; Prob_4_40 M0 ( sum_diff, carry_borrow, A, B, sel_diff); initial #4000 $finish; initial begin for (I = 0; I < 2; I = I + 1) begin sel_diff = I; for (J = 0; J < 16; J = J + 1) begin A = J; for (K = 0; K < 16; K = K + 1) begin B = K; #5 ; end end end end endmodule 4.41 module Prob_4_41 ( output reg [3: 0] sum_diff, output reg carry_borrow, input [3: 0] A, B, input sel_diff ); always @ (A, B, sel_diff) {carry_borrow, sum_diff} = sel_diff ? A - B : A + B; endmodule module t_Prob_4_41; wire [3: 0] sum_diff; wire carry_borrow; reg [3:0] A, B; reg sel_diff; integer I, J, K; Prob_4_46 M0 ( sum_diff, carry_borrow, A, B, sel_diff); initial #4000 $finish; initial begin for (I = 0; I < 2; I = I + 1) begin sel_diff = I; for (J = 0; J < 16; J = J + 1) begin A = J; for (K = 0; K < 16; K = K + 1) begin B = K; #5 ; end end end end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 87 Name 780 810 840 870 sel_diff 9 A[3:0] a b B[3:0] c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 sum_diff[3:0] 5 6 7 8 a b c d e f 0 1 2 3 4 5 6 7 8 9 b c d carry_borrow Name 2064 2094 2124 2154 sel_diff 9 A[3:0] B[3:0] d e sum_diff[3:0] c b a f 0 a b 1 2 3 4 5 6 7 8 9 a b c d e 9 8 7 6 5 4 3 2 1 0 f e d c f 0 b 1 2 a 9 carry_borrow 4.42 (a) module Xs3_Gates (input A, B, C, D, output w, x, y, z); wire B_bar, C_or_D_bar; wire CD, C_or_D; or (C_or_D, C, D); not (C_or_D_bar, C_or_D); not (B_bar, B); and (CD, C, D); not (z, D); or (y, CD, C_or_D_bar); and (w1, C_or_D_bar, B); and (w2, B_bar, C_or_D); and (w3, C_or_D, B); or (x, w1, w2); or (w, w3, A); endmodule (b) module Xs3_Dataflow (input A, B, C, D, output w, x, y, z); assign {w, x, y, z} = {A, B, C, D} + 4'b0011; endmodule (c) module Xs3_Behavior_95 (A, B, C, D, w, x, y, z); input A, B, C, D; output w, x, y, z; reg w, x, y, z; always @ (A or B or C or D) begin {w, x, y, z} = {A, B, C, D} + 4'b0011; end endmodule module Xs3_Behavior_01 (input A, B, C, D, output reg w, x, y, z); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 88 always @ (A, B, C, D) begin {w, x, y, z} = {A, B,C, D} + 4'b0011; end endmodule module t_Xs3_Converters (); reg A, B, C, D; wire w_Gates, x_Gates, y_Gates, z_Gates; wire w_Dataflow, x_Dataflow, y_Dataflow, z_Dataflow; wire w_Behavior_95, x_Behavior_95, y_Behavior_95, z_Behavior_95; wire w_Behavior_01, x_Behavior_01, y_Behavior_01, z_Behavior_01; integer k; wire [3: 0] BCD_value; wire [3: 0] Xs3_Gates = {w_Gates, x_Gates, y_Gates, z_Gates}; wire [3: 0] Xs3_Dataflow = {w_Dataflow, x_Dataflow, y_Dataflow, z_Dataflow}; wire [3: 0] Xs3_Behavior_95 = {w_Behavior_95, x_Behavior_95, y_Behavior_95, z_Behavior_95}; wire [3: 0] Xs3_Behavior_01 = {w_Behavior_01, x_Behavior_01, y_Behavior_01, z_Behavior_01}; assign BCD_value = {A, B, C, D}; Xs3_Gates M0 (A, B, C, D, w_Gates, x_Gates, y_Gates, z_Gates); Xs3_Dataflow M1 (A, B, C, D, w_Dataflow, x_Dataflow, y_Dataflow, z_Dataflow); Xs3_Behavior_95 M2 (A, B, C, D, w_Behavior_95, x_Behavior_95, y_Behavior_95, z_Behavior_95); Xs3_Behavior_01 M3 (A, B, C, D, w_Behavior_01, x_Behavior_01, y_Behavior_01, z_Behavior_01); initial #200 $finish; initial begin k = 0; repeat (10) begin {A, B, C, D} = k; #10 k = k + 1; end end endmodule 0 Name 30 60 90 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 Xs3_Gates[3:0] 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Xs3_Gates[3:0] 3 4 5 6 7 8 9 a b c Xs3_Dataflow[3:0] 3 4 5 6 7 8 9 a b c Xs3_Behavior_95[3:0] 3 4 5 6 7 8 9 a b c Xs3_Behavior_01[3:0] 3 4 5 6 7 8 9 a b c k A B C D BCD_value[3:0] w_Gates x_Gates y_Gates z_Gates 4.43 Two-channel mux with 2-bit data paths, enable, and three-state output. 4.44 module ALU (output reg [7: 0] y, input [7: 0] A, B, input [2: 0] Sel); always @ (A, B, Sel) begin y = 0; case (Sel) 3'b000: y = 8'b0; 3'b001: y = A & B; 3'b010: y = A | B; 3'b011: y = A ^ B; 3'b100: y = A + B; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 89 3'b101: 3'b110: 3'b111: endcase end y = A - B; y = ~A; y = 8'hFF; endmodule module t_ALU (); wire[7: 0]y; reg [7: 0] A, B; reg [2: 0] Sel; ALU M0 (y, A, B, Sel); initial #200 $finish; initial fork #5 begin A = 8'hAA; B = 8'h55; end // Expect y = 8'd0 #10 begin Sel = 3'b000; A = 8'hAA; B = 8'h55; end // y = 8'b000 #20 begin Sel = 3'b001; A = 8'hAA; B = 8'hAA; end // y = A & B #30 begin Sel = 3'b001; A = 8'h55; B = 8'h55; end // y = A & B #40 begin Sel = 3'b010; A = 8'h55; B = 8'h55; end // y = A | B #50 begin Sel = 3'b010; A = 8'hAA; B = 8'hAA; end // y = A | B #60 begin Sel = 3'b011; A = 8'h55; B = 8'h55; end // y = A ^ B #70 begin Sel = 3'b011; A = 8'hAA; B = 8'h55; end // y = A ^ B #80 begin Sel = 3'b100; A = 8'h55; B = 8'h00; end // y = A + B #90 begin Sel = 3'b100; A = 8'hAA; B = 8'h55; end // y = A + B #110 begin Sel = 3'b101; A = 8'hAA; B = 8'h55; end // y = A – B #120 begin Sel = 3'b101; A = 8'h55; B = 8'hAA; end // y = A – B #130 begin Sel = 3'b110; A = 8'hFF; end // y = ~A #140 begin Sel = 3'b110; A = 8'd0; end // y = ~A #150 begin Sel = 3'b110; A = 8'hFF; end // y = ~A #160 begin Sel = 3'b111; end // y = 8'hFF join endmodule Name 0 60 001 Sel[2:0] aa 010 55 aa B[7:0] 55 aa 55 aa y[7:0] 00 aa 55 aa A[7:0] Expect y = 8'd0 Expect y = 8'hAA = 8'1010_1010 Expect y = 8'h55 = 8'b0101_0101 Expect y = 8'h55 = 8'b0101_0101 Expect y = 8'hAA = 8'b1010_1010 Expect y = 8'd0 Expect y = 8'hFF = 8'b1111_1111 Expect y = 8'h55 = 8'b0101_0101 Expect y = 8'hFF = 8'b1111_1111 Expect y = 8'h55 = 8'b0101_0101 Expect y = 8'hab = 8'b1010_1011 Expect y = 8'd0 Expect y = 8'hFF = 8'b1111_1111 Expect y = 8'd0 Expect y = 8'hFF = 8'b1111_1111 120 011 55 100 aa 55 00 ff 101 55 aa 00 55 55 180 ff 55 110 ff 111 00 ff aa 55 ab 00 ff 00 ff Note that the subtraction operator performs 2's complement subtraction. So 8'h55 – 8'hAA adds the 2's complement of 8'hAA to 8'h55 and gets 8'hAB. The sign bit is not included in the model, but hand calculation shows that the 9th bit is 1, indicating that the result of the operation is negative. The magnitude of the result can be obtained by taking the 2's complement of 8'hAB. 4.45 module priority_encoder_beh (output reg X, Y, V, input D0, D1, D2, D3); // V2001 always @ (D0, D1, D2, D3) begin X = 0; Y = 0; V = 0; casex ({D0, D1, D2, D3}) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 90 4'b0000: 4'b1000: 4'bx100: 4'bxx10: 4'bxxx1: default: endcase end endmodule {X, Y, V} = 3'bxx0; {X, Y, V} = 3'b001; {X, Y, V} = 3'b011; {X, Y, V} = 3'b101; {X, Y, V} = 3'b111; {X, Y, V} = 3'b000; module t_priority_encoder_beh (); // V2001 wire X, Y, V; reg D0, D1, D2, D3; integer k; priority_encoder_beh M0 (X, Y, V, D0, D1, D2, D3); initial #200 $finish; initial begin k = 32'bx; #10 for (k = 0; k <= 16; k = k + 1) #10 {D0, D1, D2, D3} = k; end endmodule Name 0 k 60 0 1 2 3 4 5 120 6 7 8 9 10 11 12 180 13 14 15 16 17 D0 D1 D2 D3 X Y V Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 4.46 91 (a) F = Σ(0, 2, 5, 7, 11, 14) See code below. (b) From prob 4.32: F = Π (3, 8, 12) = (A' + B' + C + D)(A + B' + C' + D')(A + B + C' + D') F' = ABC'D' + A'BCD + A'B'CD = Σ(12, 7, 3) F = Σ(0, 1, 2, 4, 5, 6, 8, 9, 10, 11, 13, 14, 15) module Prob_4_46a (output F, input A, B, C, D); assign F = (~A&~B&~C&~D) | (~A&~B&C&~D) | (~A&B&~C&D) | (~A&B&C&D) | (A&~B&C&D) | (A&B&C&~D); endmodule module Prob_4_46b (output F, input A, B, C, D); assign F = (~A&~B&~C&~D) | (~A&~B&~C&D) | (~A&~B&C&~D) | (~A&B&~C&~D) | (~A&B&~C&D) | (~A&B&C&~D) | (A&~B&~C&~D) | (A&~B&~C&D) | (A&~B&C&~D) | (A&~B&C&D) | (A&B&~C&D) | (A&B&C&~D) | (A&B&C&D); endmodule module t_Prob_4_46a (); wire F_a, F_b; reg A, B, C, D; integer k; Prob_4_46a M0 (F_a, A, B, C, D); Prob_4_46b M1 (F_b, A, B, C, D); initial #200 $finish; initial begin k = 0; #10 repeat (15) begin {A, B, C, D} = k; #10 k = k + 1; end end endmodule Name 0 k 60 0 1 2 3 4 5 120 6 7 8 9 10 11 12 180 13 14 15 16 17 D0 D1 D2 D3 X Y V Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 92 4.47 module Add_Sub_4_bit_Dataflow ( output [3: 0] S, output C, V, input [3: 0] A, B, input M ); wire C3; assign {C3, S[2: 0]} = A[2: 0] + ({M, M, M} ^ B[2: 0]) + M; assign {C, S[3]} = A[3] + M ^ B[3] + C3; assign V = C ^ C3; endmodule module t_Add_Sub_4_bit_Dataflow (); wire [3: 0] S; wire C, V; reg [3: 0] A, B; reg M; Add_Sub_4_bit_Dataflow M0 (S, C, V, A, B, M); initial #100 $finish; initial fork #10 M = 0; #10 A = 4'hA; #10 B = 4'h5; #50 M = 1; #70 B = 4'h3; join endmodule Name 0 50 A[3:0] x B[3:0] x 100 a 5 3 M S[3:0] x f 5 7 C 4.48 module ALU_3state (output [7: 0] y_tri, input [7: 0] A, B, input [2: 0] Sel, input En); reg [7: 0] y; assign y_tri = En ? y: 8'bz; always @ (A, B, Sel) begin y = 0; case (Sel) 3'b000: y = 8'b0; 3'b001: y = A & B; 3'b010: y = A | B; 3'b011: y = A ^ B; 3'b100: y = A + B; 3'b101: y = A - B; 3'b110: y = ~A; 3'b111: y = 8'hFF; endcase end Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 93 endmodule module t_ALU_3state (); wire[7: 0] y; reg [7: 0] A, B; reg [2: 0] Sel; reg En; ALU_3state M0 (y, A, B, Sel, En); initial #200 $finish; initial fork #5 En = 1; #5 begin A = 8'hAA; B = 8'h55; end // Expect y = 8'd0 #10 begin Sel = 3'b000; A = 8'hAA; B = 8'h55; end // y = 8'b000 Expect y = 8'd0 #20 begin Sel = 3'b001; A = 8'hAA; B = 8'hAA; end // y = A & B Expect y = 8'hAA = 8'1010_1010 #30 begin Sel = 3'b001; A = 8'h55; B = 8'h55; end // y = A & B Expect y = 8'h55 = 8'b0101_0101 #40 begin Sel = 3'b010; A = 8'h55; B = 8'h55; end // y = A | B Expect y = 8'h55 = 8'b0101_0101 #50 begin Sel = 3'b010; A = 8'hAA; B = 8'hAA; end // y = A | BExpect y = 8'hAA = 8'b1010_1010 #60 begin Sel = 3'b011; A = 8'h55; B = 8'h55; end // y = A ^ B Expect y = 8'd0 #70 begin Sel = 3'b011; A = 8'hAA; B = 8'h55; end // y = A ^ B Expect y = 8'hFF = 8'b1111_1111 #80 begin Sel = 3'b100; A = 8'h55; B = 8'h00; end // y = A + B Expect y = 8'h55 = 8'b0101_0101 #90 begin Sel = 3'b100; A = 8'hAA; B = 8'h55; end // y = A + B Expect y = 8'hFF = 8'b1111_1111 #100 En = 0; #115 En = 1; #110 begin Sel = 3'b101; A = 8'hAA; B = 8'h55; end // y = A – B Expect y = 8'h55 = 8'b0101_0101 #120 begin Sel = 3'b101; A = 8'h55; B = 8'hAA; end // y = A – B Expect y = 8'hab = 8'b1010_1011 #130 begin Sel = 3'b110; A = 8'hFF; end // y = ~A Expect y = 8'd0 #140 begin Sel = 3'b110; A = 8'd0; end // y = ~A Expect y = 8'hFF = 8'b1111_1111 #150 begin Sel = 3'b110; A = 8'hFF; end // y = ~A Expect y = 8'd0 #160 begin Sel = 3'b111; end // y = 8'hFF Expect y = 8'hFF = 8'b1111_1111 join endmodule 4.49 // See Problem 4.1 module Problem_4_49_Gates (output F1, F2, input A, B, C, D); wire A_bar = !A; wire B_bar = !B; and (T1, B_bar, C); and (T2, A_bar, B); or (T3, A, T1); xor (T4, T2, D); or (F1, T3, T4); or (F2, T2, D); endmodule module Problem_4_49_Boolean_1 (output F1, F2, input A, B, C, D); wire A_bar = !A; wire B_bar = !B; wire T1 = B_bar && C; wire T2 = A_bar && B; wire T3 = A || T1; wire T4 = T2 ^ D; assign F1 = T3 || T4; assign F2 = T2 || D; endmodule module Problem_4_49_Boolean_2(output F1, F2, input A, B, C, D); assign F1 = A || (!B && C) || (B && (!D)) || (!B && D); assign F2 = ((!A) && B) || D; endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 94 module t_Problem_4_49; reg A, B, C, D; wire F1_Gates, F2_Gates; wire F1_Boolean_1, F2_Boolean_1; wire F1_Boolean_2, F2_Boolean_2; Problem_4_48_Gates M0 (F1_Gates, F2_Gates, A, B, C, D); Problem_4_48_Boolean_1 M1 (F1_Boolean_1, F2_Boolean_1, A, B, C, D); Problem_4_48_Boolean_2 M2 (F1_Boolean_2, F2_Boolean_2, A, B, C, D); initial #100 $finish; integer K; initial begin for (K = 0; K < 16; K = K + 1) begin {A, B, C, D} = K; #5; end end endmodule 4.50 (a) 84-2-1 to BCD code converter // See Problem 4.8 and Table 1.5. // Verilog 1995 // module Prob_4_50a (Code_BCD, Code84_m2_m1); // output [3: 0] Code_BCD; // input [3:0]; // reg [3: 0] Code_BCD; // ... // Verilog 2001, 2005 module Prob_4_50a (output reg [3: 0] Code_BCD, input [3: 0] Code_84_m2_m1); always @ (Code_84_m2_m1) case (Code_84_m2_m1) 4'b0000: Code_BCD = 4'b0000; 4'b0111: Code_BCD = 4'b0001; 4'b0110: Code_BCD = 4'b0010; 4'b0101: Code_BCD = 4'b0011; 4'b0100: Code_BCD = 4'b0100; 4'b1011: Code_BCD = 4'b0101; 4'b1010: Code_BCD = 4'b0110; 4'b1001: Code_BCD = 4'b0111; 4'b1000: Code_BCD = 4'b1000; 4'b1111: Code_BCD = 4'b1001; 4'b0001: Code_BCD = 4'b1010; 4'b0010: Code_BCD = 4'b1011; 4'b0011: Code_BCD = 4'b1100; 4'b1100: Code_BCD= 4'b1101; 4'b1101: Code_BCD = 4'b1110; 4'b1110: Code_BCD = 4'b1111; endcase endmodule // always @ (A or B or C or D) // 0 // 1 // 2 // 3 // 4 // 5 // 6 // 7 // 8 // 9 // 10 // 11 // 12 // 13 // 14 // 15 module t_Prob_4_50a; wire [3: 0] Code_BCD; reg [3: 0]; Code_84_m2_m1; integer K; Prob_4_50a M0 ( Code_BCD, Code_84_m2_m1); // Unit under test (UUT) initial #100 $finish; initial begin for (K = 0; K < 16; K = K + 1) begin Code_84_m2_m1 = K; #5 ; end end Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 95 endmodule (b) 84-2-1 to Gray code converter module Prob_4_50b (output reg [3: 0] Code_BCD, input [3: 0] Code_84_m2_m1); always @ (Code_84_m2_m1) case (Code_84_m2_m1) 4'b0000: Code_Gray = 4'b0000; 4'b0111: Code_Gray = 4'b0001; 4'b0110: Code_Gray = 4'b0011; 4'b0101: Code_Gray = 4'b0010; 4'b0100: Code_Gray = 4'b0110; 4'b1011: Code_Gray = 4'b0111; 4'b1010: Code_Gray = 4'b0101; 4'b1001: Code_Gray = 4'b0100; 4'b1000: Code_Gray = 4'b1100; 4'b1111: Code_Gray = 4'b1101; 4'b0001: Code_Gray = 4'b1111; 4'b0010: Code_Gray = 4'b1110; 4'b0011: Code_Gray = 4'b1010; 4'b1100: Code_Gray= 4'b1011; 4'b1101: Code_Gray = 4'b1001; 4'b1110: Code_Gray = 4'b1000; endcase endmodule // 0 // 1 // 2 // 3 // 4 // 5 // 6 // 7 // 8 // 9 // 10 // 11 // 12 // 13 // 14 // 15 module t_Prob_4_50b; wire [3: 0] Code_Gray; reg [3: 0] Code_84_m2_m1; integer K; Prob_4_50b M0 (Code_Gray, Code_84_m2_m1); // Unit under test (UUT) initial #100 $finish; initial begin for (K = 0; K < 16; K = K + 1) begin Code_84_m2_m1 = K; #5 ; end end endmodule 4.51 Assume that that the LEDs are asserted when the output is high. module Seven_Seg_Display_V2001 ( output reg [6: 0] Display, input [3: 0] BCD ); // parameter parameter parameter parameter parameter parameter BLANK ZERO ONE TWO THREE FOUR abc_defg = 7'b000_0000; = 7'b111_1110; = 7'b011_0000; = 7'b110_1101; = 7'b111_1001; = 7'b011_0011; // h7e // h30 // h6d // h79 // h33 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 96 parameter parameter parameter parameter parameter FIVE SIX SEVEN EIGHT NINE = 7'b101_1011; = 7'b101_1111; = 7'b111_0000; = 7'b111_1111; = 7'b111_1011; // h5b // h5f // h70 // h7f // h7b always @ (BCD) case (BCD) 0: Display = ZERO; 1: Display = ONE; 2: Display = TWO; 3: Display = THREE; 4: Display = FOUR; 5: Display = FIVE; 6: Display = SIX; 7: Display = SEVEN; 8: Display = EIGHT; 9: Display = NINE; default: Display = BLANK; endcase endmodule module t_Seven_Seg_Display_V2001 (); wire [6: 0] Display; reg [3: 0] BCD; parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter BLANK ZERO ONE TWO THREE FOUR FIVE SIX SEVEN EIGHT NINE = 7'b000_0000; = 7'b111_1110; = 7'b011_0000; = 7'b110_1101; = 7'b111_1001; = 7'b011_0011; = 7'b101_1011; = 7'b001_1111; = 7'b111_0000; = 7'b111_1111; = 7'b111_1011; // h7e // h30 // h6d // h79 // h33 // h5b // h1f // h70 // h7f // h7b initial #120 $finish; initial fork #10 BCD = 0; #20 BCD = 1; #30 BCD = 2; #40 BCD = 3; #50 BCD = 4; #60 BCD = 5; #70 BCD = 6; #80 BCD = 7; #90 BCD = 8; #100 BCD = 9; join Seven_Seg_Display_V2001 M0 (Display, BCD); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 97 Name 0 60 120 BCD[3:0] x 0 1 2 3 4 5 6 7 8 9 Display[6:0] xx 7e 30 6d 79 33 5b 5f 70 7f 7b Alternative with continuous assignments (dataflow): module Seven_Seg_Display_V2001_CA ( output [6: 0] Display, input [3: 0] BCD ); // abc_defg parameter BLANK = 7'b000_0000; parameter ZERO = 7'b111_1110; parameter ONE = 7'b011_0000; parameter TWO = 7'b110_1101; parameter THREE = 7'b111_1001; parameter FOUR = 7'b011_0011; parameter FIVE = 7'b101_1011; parameter SIX = 7'b101_1111; parameter SEVEN = 7'b111_0000; parameter EIGHT = 7'b111_1111; parameter NINE = 7'b111_1011; wire A, B, C, D, a, b, c, d, e, f, g; // h7e // h30 // h6d // h79 // h33 // h5b // h5f // h70 // h7f // h7b assign A = BCD[3]; assign B = BCD[2]; assign C = BCD[1]; assign D = BCD[0]; assign Display = {a,b,c,d,e,f,g}; assign a = (~A)&C | (~A)&B&D | (~B)&(~C)&(~D) | A & (~B)&(~C); assign b = (~A)&(~B) | (~A)&(~C)&(~D) | (~A)&C&D | A&(~B)&(~C); assign c = (~A)&B | (~A)&D | (~B)&(~C)&(~D) | A&(~B)&(~C); assign d = (~A)&C&(~D) | (~A)&(~B)&C | (~B)&(~C)&(~D) | A&(~B)&(~C) | (~A)&B&(~C)&D; assign e = (~A)&C&(~D) | (~B)&(~C)&(~D); assign f = (~A)&B&(~C) | (~A)&(~C)&(~D) | (~A)&B&(~D) | A&(~B)&(~C); assign g = (~A)&C&(~D) | (~A)&(~B)&C | (~A)&B&(~C) | A&(~B)&(~C); endmodule module t_Seven_Seg_Display_V2001_CA (); wire [6: 0] Display; reg [3: 0] BCD; parameter BLANK = 7'b000_0000; parameter ZERO = 7'b111_1110; // h7e parameter ONE = 7'b011_0000; // h30 parameter TWO = 7'b110_1101; // h6d parameter THREE = 7'b111_1001; // h79 parameter FOUR = 7'b011_0011; // h33 parameter FIVE = 7'b101_1011; // h5b parameter SIX = 7'b001_1111; // h1f parameter SEVEN = 7'b111_0000; // h70 parameter EIGHT = 7'b111_1111; // h7f parameter NINE = 7'b111_1011; // h7b initial #120 $finish; initial fork Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 98 #10 BCD = 0; #20 BCD = 1; #30 BCD = 2; #40 BCD = 3; #50 BCD = 4; #60 BCD = 5; #70 BCD = 6; #80 BCD = 7; #90 BCD = 8; #100 BCD = 9; join Seven_Seg_Display_V2001_CA M0 (Display, BCD); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 4.52 99 (a) Incrementer for unsigned 4-bit numbers module Problem_4_52a_Data_Flow (output [3: 0] sum, output carry, input [3: 0] A); assign {carry, sum} = A + 1; endmodule module t_Problem_4_52a_Data_Flow; wire [3: 0] sum; wire carry; reg [3: 0] A; Problem_4_52a_Data_Flow M0 (sum, carry, A); initial # 100 $finish; integer K; initial begin for (K = 0; K < 16; K = K + 1) begin A = K; #5; end end endmodule (b) Decrementer for unsigned 4-bit numbers module Problem_4_52b_Data_Flow (output [3: 0] diff, output borrow, input [3: 0] A); assign {borrow, diff} = A - 1; endmodule module t_Problem_4_52b_Data_Flow; wire [3: 0] diff; wire borrow; reg [3: 0] A; Problem_4_52b_Data_Flow M0 (diff, borrow, A); initial # 100 $finish; integer K; initial begin for (K = 0; K < 16; K = K + 1) begin A = K; #5; end end endmodule Name 0 30 60 90 A[3:0] 0 1 2 3 4 5 6 7 8 9 a b c d e f diff[3:0] f 0 1 2 3 4 5 6 7 8 9 a b c d e borrow Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 4.53 100 // BCD Adder module Problem_4_53_BCD_Adder ( output Output_carry, output [3: 0] Sum, input [3: 0] Addend, Augend, input Carry_in); supply0 gnd; wire [3: 0] Z_Addend; wire Carry_out; wire C_out; assign Z_Addend = {1'b0, Output_carry, Output_carry, 1'b0}; wire [3: 0] Z_sum; and (w1, Z_sum[3], Z_sum[2]); and (w2, Z_sum[3], Z_sum[1]); or (Output_carry, Carry_out, w1, w2); Adder_4_bit M0 (Carry_out, Z_sum, Addend, Augend, Carry_in); Adder_4_bit M1 (C_out, Sum, Z_Addend, Z_sum, gnd); endmodule module Adder_4_bit (output carry, output [3:0] sum, input [3: 0] a, b, input c_in); assign {carry, sum} = a + b + c_in; endmodule module t_Problem_4_53_Data_Flow; wire [3: 0] Sum; wire Output_carry; reg [3: 0] Addend, Augend; reg Carry_in; Problem_4_53_BCD_Adder M0 (Output_carry, Sum, Addend, Augend, Carry_in); initial # 1500 $finish; integer i, j, k; initial begin for (i = 0; i <= 1; i = i + 1) begin Carry_in = i; #5; for (j = 0; j <= 9; j = j +1) begin Addend = j; #5; for (k = 0; k <= 9; k = k + 1) begin Augend = k; #5; end end end end endmodule Name 68 98 158 1 Addend[3:0] Augend[3:0] 128 188 2 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 9 3 0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 0 9 0 1 2 3 4 5 3 4 5 6 7 8 Carry_in Sum[3:0] 0 1 1 2 Output_carry Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 4.54 101 (a) 9s Complement of BCD module Nines_Complementer ( // V2001 output reg [3: 0] Word_9s_Comp, input [3: 0] Word_BCD ); always @ (Word_BCD) begin Word_9s_Comp = 4'b0; case (Word_BCD) 4'b0000: Word_9s_Comp = 4'b1001; // 0 to 9 4'b0001: Word_9s_Comp = 4'b1000; // 1 to 8 4'b0010: Word_9s_Comp = 4'b0111; // 2 to 7 4'b0011: Word_9s_Comp = 4'b0110; // 3 to 6 4'b0100: Word_9s_Comp = 4'b0101; // 4 to 5 4'b0101: Word_9s_Comp = 4'b0100; // 5 to 4 4'b0110: Word_9s_Comp = 4'b0011; // 6 to 3 4'b0111: Word_9s_Comp = 4'b0010; // 7 to 2 4'b1000: Word_9s_Comp = 4'b0001; // 8 to 1 4'b1001: Word_9s_Comp = 4'b0000; // 9 to 0 default: Word_9s_Comp = 4'b1111; // Error detection endcase end endmodule module t_Nines_Complementer (); wire [3: 0] Word_9s_Comp; reg [3: 0] Word_BCD; Nines_Complementer M0 (Word_9s_Comp, Word_BCD); initial #11$finish; initial fork Word_BCD = 0; #10 Word_BCD = 1; #20 Word_BCD = 2; #30 Word_BCD = 3; #40 Word_BCD = 4; #50 Word_BCD = 5; #60 Word_BCD = 6; #70 Word_BCD = 7; #20 Word_BCD = 8; #90 Word_BCD = 9; #100 Word_BCD = 4'b1100; join endmodule Name Word_BCD[3:0] Word_9s_Comp[3:0] // Confirm error detection 0 60 0 1 2 3 4 5 6 7 9 9 8 7 6 5 4 3 2 0 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 102 (b) 9s complement of Gray Code module Nines_Complementer ( // V2001 output reg [3: 0] Word_9s_Comp, input [3: 0] Word_Gray ); always @ (Word_Gray) begin Word_9s_Comp = 4'b0; case (Word_BCD) 4'b0000: Word_9s_Comp = 4'b1101; // 0 to 9 4'b0001: Word_9s_Comp = 4'b1100; // 1 to 8 4'b0010: Word_9s_Comp = 4'b0100; // 2 to 7 4'b0011: Word_9s_Comp = 4'b0101; // 3 to 6 4'b0100: Word_9s_Comp = 4'b0111; // 4 to 5 4'b0101: Word_9s_Comp = 4'b0110; // 5 to 4 4'b0110: Word_9s_Comp = 4'b0010; // 6 to 3 4'b0111: Word_9s_Comp = 4'b0011; // 7 to 2 4'b1000: Word_9s_Comp = 4'b0001; // 8 to 1 4'b1001: Word_9s_Comp = 4'b0000; // 9 to 0 default: Word_9s_Comp = 4'b1111; // Error detection endcase end endmodule module t_Nines_Complementer (); wire [3: 0] Word_9s_Comp; reg [3: 0] Word_Gray; Nines_Complementer M0 (Word_9s_Comp, Word_Gray); initial #11$finish; initial fork Word_Gray = 0; #10 Word_Gray = 1; #20 Word_Gray = 2; #30 Word_Gray = 3; #40 Word_Gray = 4; #50 Word_Gray = 5; #60 Word_Gray = 6; #70 Word_Gray = 7; #20 Word_Gray = 8; #90 Word_Gray = 9; #100 Word_Gray = 4'b1100; join endmodule // Confirm error detection Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 103 4.55 From Problem 4.19: Mode = 0 FOR Add Mode = 1 for Subtract B3 B2 B1 B0 9's Complementer (See Problem 4.18) Select = 1 Select Select = 0 Quadruple 2 x 1 MUX A3 A2 A1 A0 Cin BCD Adder (See Fig. 4.14) // BCD Adder – Subtractor module Problem_4_55_BCD_Adder_Subtractor ( output [3: 0] BCD_Sum_Diff, output Carry_Borrow, input [3: 0] B, A, input Mode ); wire [3: 0] Word_9s_Comp, mux_out; Nines_Complementer M0 (Word_9s_Comp, B); Quad_2_x_1_mux M2 (mux_out, Word_9s_Comp, B, Mode); BCD_Adder M1 (Carry_Borrow, BCD_Sum_Diff, mux_out, A, Mode); endmodule module Nines_Complementer ( // V2001 output reg [3: 0] Word_9s_Comp, input [3: 0] Word_BCD ); always @ (Word_BCD) begin Word_9s_Comp = 4'b0; case (Word_BCD) 4'b0000: Word_9s_Comp = 4'b1001; // 0 to 9 4'b0001: Word_9s_Comp = 4'b1000; // 1 to 8 4'b0010: Word_9s_Comp = 4'b0111; // 2 to 7 4'b0011: Word_9s_Comp = 4'b0110; // 3 to 6 4'b0100: Word_9s_Comp = 4'b1001; // 4 to 5 4'b0101: Word_9s_Comp = 4'b0100; // 5 to 4 4'b0110: Word_9s_Comp = 4'b0011; // 6 to 3 4'b0111: Word_9s_Comp = 4'b0010; // 7 to 2 4'b1000: Word_9s_Comp = 4'b0001; // 8 to 1 4'b1001: Word_9s_Comp = 4'b0000; // 9 to 0 default: Word_9s_Comp = 4'b1111; // Error detection endcase end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 104 module Quad_2_x_1_mux (output reg [3: 0] mux_out, input [3: 0] b, a, input select); always @ (a, b, select) case (select) 0: mux_out = a; 1: mux_out = b; endcase endmodule module BCD_Adder ( output Output_carry, output [3: 0] Sum, input [3: 0] Addend, Augend, input Carry_in); supply0 gnd; wire [3: 0] Z_Addend; wire Carry_out; wire C_out; assign Z_Addend = {1'b0, Output_carry, Output_carry, 1'b0}; wire [3: 0] Z_sum; and (w1, Z_sum[3], Z_sum[2]); and (w2, Z_sum[3], Z_sum[1]); or (Output_carry, Carry_out, w1, w2); Adder_4_bit M0 (Carry_out, Z_sum, Addend, Augend, Carry_in); Adder_4_bit M1 (C_out, Sum, Z_Addend, Z_sum, gnd); endmodule module Adder_4_bit (output carry, output [3:0] sum, input [3: 0] a, b, input c_in); assign {carry, sum} = a + b + c_in; endmodule module t_Problem_4_55_BCD_Adder_Subtractor(); wire [3: 0] BCD_Sum_Diff; wire Carry_Borrow; reg [3: 0] B, A; reg Mode; Problem_4_55_BCD_Adder_Subtractor M0 (BCD_Sum_Diff, Carry_Borrow, B, A, Mode); initial #1000 $finish; integer J, K, M; initial begin for (M = 0; M < 2; M = M + 1) begin for (J = 0; J < 10; J = J + 1) begin for (K = 0; K < 10; K = K + 1) begin A = J; B = K; Mode = M; #5 ; end end end end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 105 Name 258 288 318 348 0 M 5 A[3:0] 6 7 B[3:0] 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 Word_9s_Comp[3:0] 7 6 9 4 3 2 1 0 9 8 7 6 9 4 3 2 1 0 9 8 7 3 6 mux_out[3:0] 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 BCD_Sum_Diff[3:0] 7 8 9 0 1 2 3 4 6 7 8 9 0 1 2 3 4 5 7 8 9 0 Carry_Borrow Note: For subtraction, Carry_Borrow = 1 indicates a positive result; Carry_Borrow = 0 indicates a negative result. Name 768 798 828 858 1 M 5 A[3:0] 6 7 B[3:0] 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 Word_9s_Comp[3:0] 9 4 3 2 1 0 9 8 7 6 9 4 3 2 1 0 9 8 7 6 9 4 mux_out[3:0] 9 4 3 2 1 0 9 8 7 6 9 4 3 2 1 0 9 8 7 6 9 4 BCD_Sum_Diff[3:0] 5 0 9 8 7 5 4 3 6 1 0 9 8 6 5 4 7 2 6 7 Carry_Borrow Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 106 4.56 assign match = (A == B); // Assumes reg [3: 0] A, B; 4.57 // Priority encoder (See Problem 4.29) // Caution: do not confuse logic value x with identifier x. // Verilog 1995 module Prob_4_57 (x, y, v, D3, D2, D1, D0); output x, y, v; input D3, D2, D1, D0; reg x, y, v; ... // Verilog 2001, 2005 module Prob_4_57 (output reg x, y, v, input D3, D2, D1, D0); always @ (D3, D2, D1, D0) begin // always @ (D3 or D2 or D1 or D0) x = 0; y = 0; v = 0; casex ({D3, D2, D1, D0}) 4'b0000: {x, y, v} = 3'bxx0; 4'bxxx1: {x, y, v} = 3'b001; 4'bxx10: {x, y, v} = 3'b011; 4'bx100: {x, y, v} = 3'b101; 4'b1000: {x, y, v} = 3'b110; endcase end endmodule module t_Prob_4_57; wire x, y, v; reg D3, D2, D1, D0; integer K; Prob_4_57 M0 (x, y, v, D3, D2, D1, D0); initial #100 $finish; initial begin for (K = 0; K < 16; K = K + 1) begin {D3, D2, D1, D0} = K; #5 ; end end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 4.58 107 (a) //module shift_right_by_3_V2001 (output [31: 0] sig_out, input [31: 0] sig_in); // assign sig_out = sig_in >>> 3; //endmodule module shift_right_by_3_V1995 (output reg [31: 0] sig_out, input [31: 0] sig_in); always @ (sig_in) sig_out = {sig_in[31], sig_in[31], sig_in[31], sig_in[31: 3]}; endmodule module t_shift_right_by_3 (); wire [31: 0] sig_out_V1995; wire [31: 0] sig_out_V2001; reg [31: 0] sig_in; //shift_right_by_3_V2001 M0 (sig_out_V2001, sig_in); shift_right_by_3_V1995 M1 (sig_out_V1995, sig_in); integer k; initial #1000 $finish; initial begin sig_in = 32'hf000_0000; #100 sig_in = 32'h8fff_ffff; #500 sig_in = 32'h0fff_ffff; end endmodule Name 609 619 629 sig_in[31:0] 00001111111111111111111111111111 sig_out_V1995[31:0] 00000001111111111111111111111111 Name 34 44 639 54 sig_in[31:0] 11110000000000000000000000000000 sig_out_V1995[31:0] 11111110000000000000000000000000 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 64 108 (b) //module shift_left_by_3_V2001 (output [31: 0] sig_out, input [31: 0] sig_in); assign sig_out = sig_in <<< 3; //module shift_left_by_3_V1995 (output reg [31: 0] sig_out, input [31: 0] sig_in); //always @ (sig_in) // sig_out = {sig_in[31: 3], 3'b0}; endmodule module t_shift_left_by_3 (); wire [31: 0] sig_out_V1995; wire [31: 0] sig_out_V2001; reg [31: 0] sig_in; shift_left_by_3_V2001 M0 (sig_out_V2001, sig_in); integer k; initial #1000 $finish; initial begin sig_in = 32'hf000_0000; #100 sig_in = 32'h8fff_ffff; #500 sig_in = 32'h0fff_ffff; end endmodule Name 0 50 100 150 sig_in[31:0] xxxxxxxx 0000000f sig_out_V1995[31:0] xxxxxxxx 00000078 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 109 4.59 module BCD_to_Decimal (output reg [3: 0] Decimal_out, input [3: 0] BCD_in); always @ (BCD_in) begin Decimal_out = 0; case (BCD_in) 4'b0000: Decimal_out = 0; 4'b0001: Decimal_out = 1; 4'b0010: Decimal_out = 2; 4'b0011: Decimal_out = 3; 4'b0100: Decimal_out = 4; 4'b0101: Decimal_out = 5; 4'b0110: Decimal_out = 6; 4'b0111: Decimal_out = 7; 4'b1000: Decimal_out = 8; 4'b1001: Decimal_out = 9; default: Decimal_out = 4'bxxxx; endcase end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 110 4.60 module Even_Parity_Checker_4 (output P, C, input x, y, z); xor (w1, x, y); xor (P, w1, z); xor (C, w1, w2); xor (w2, z, P); endmodule See Problem 4.62 for testbench and waveforms. 4.61 module Even_Parity_Checker_4 (output P, C, input x, y, z); assign w1 = x ^ y; assign P = w1 ^ z; assign C = w1 ^ w2; assign w2 = z ^ P; endmodule 0 Name 140 280 420 x y z P C Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 111 4.62 A0 A1 A2 3x8 Decoder 8 D0 - D7 E 3x8 Decoder 8 D8 - D15 E A3 0 20 2x4 Decoder A4 21 E 1 2 3 3x8 Decoder 8 3x8 Decoder 8 D16 - D23 E E D24 - D31 E module Decoder_3x8 (output D7, D6, D5, D4, D3, D2, D1, D0, input in2, in1, in0, E); not (in2_bar, in2); not (in1_bar, in1); not (in0_bar, in0); and (D0, in2_bar, in1_bar, in0_bar, E); and (D1, in2_bar, in1_bar, in0, E); and (D2, in2_bar, in1, in0_bar, E); and (D3, in2_bar, in1, in0, E); and (D4, in2, in1_bar, in0_bar, E); and (D5, in2, in1_bar, in0, E); and (D6, in2, in1, in0_bar, E); and (D7, in2, in1, in0, E); endmodule module Decoder_5x32 ( output D31, D30, D29, D28, D27, D26, D25, D24, D23, D22, D21, D20, D19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, input A4, A3, A2, A1, A0, E; wire E3, E2, E1, E0; Decoder_3x8 M0 (D7, D6, D5, D4, D3, D2, D1, D0, A2, aA1, A0, E0); Decoder_3x8 M1 (D15, D14, D13, D12, D11, D10, D9, D8, A2, A1, A0, E1); Decoder_3x8 M2 (D23, D22, D21, D20, D19, D18, D17, D16, in2, in1, in0, E2); Decoder_3x8 M3 (D31, D30, D29, D28, D27, D26, D25, D24, A2, A1, A0, E3); Decoder_2x4 M4 (E3, E2, E1, E0, A4, A3, E); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 112 4.63 A0 20 A1 1 2 20 1 2 A2 4 D0 - D3 E 2x4 Decoder 4 D4 - D7 E 0 20 2x4 Decoder A3 2x4 Decoder 21 E 1 2 20 3 21 2x4 Decoder 4 2x4 Decoder 4 D8 - D11 E E 20 21 D12 - D15 E module Decoder_2x4 (output D3, D2, D1, D0, input in1, in0, E); not (in1_bar, in1); not (in0_bar, in0); and (D0, in1_bar, in0_bar, E); and (D1, in1_bar, in0, E); and (D2, in1, in0_bar, E); and (D3, in1, in0, E); endmodule module Decoder_4x16 ( output D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, input A3, A2, A1, A0, E); wire E3, E2, E1, E0; Decoder_2x4 M0 (output D3, D2, D1, D0, input in1, in0, E0); Decoder_2x4 M1 (output D7, D6, D5, D4, input in1, in0, E1); Decoder_2x4 M2 (output D11, D10, D9, D8, input in1, in0, E2); Decoder_2x4 M3 (output D15, D14, D13, D12, input in1, in0, E3); Decoder_2x4 M4 (output E3, E2, E1, E0, input A3, A2, E); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 113 4.64 Inputs Outputs D0 D1 D2 D3 D4 D5 D6 D7 x y z V 0 1 x x x x x x x x 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 x x x x x x 0 0 0 1 x x x x x 0 0 0 0 1 x x x x 0 0 0 0 0 1 x x x 0 0 0 0 0 0 1 x x 0 0 0 0 0 0 0 1 x 0 0 0 0 0 0 0 0 1 If D2 = 1, D6 = 1, all others = 0 Output xyz = 100 and V = 1 x 0 0 1 1 0 0 0 1 x 0 1 0 1 0 1 0 1 module Prob_4_64 (output x, y, x, V, input, D0, D1, D2, D3, D4,D5 D6, D7); always @( D0, D1, D2, D3, D4,D5 D6, D7) case({D0, D1, D2, D3, D4,D5 D6, D7}) 8'b0000_0000: {x, y, x, V} = 4'bxxx0; 8'b1000_0000: {x, y, x, V} = 4'b0001; 8'b0100_0000: {x, y, x, V} = 4'b0011; 8'b0010_0000: {x, y, x, V} = 4'b0101; 8'b0001_0000: 8'b0000_1000: 8'b0000_0100: 8'b0000_0010: 8'b0000_0001: default: endcase endmodule {x, y, x, V} = 4'b0111; {x, y, x, V} = 4'b1001; {x, y, x, V} = 4'b1011; {x, y, x, V} = 4'b1001; {x, y, x, V} = 4'b1111; {x, y, x, V} = 4'b1010; // Use for error detection Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 114 4.65 s0 s1 s2 s3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s0 s1 s2 0 1 2 3 4 5 6 7 s0 s1 s2 0 1 2 3 4 5 6 7 8x1 MUX s 0 1 2x1 MUX y 8x1 MUX module Mux_2x1 ( output y_out, input in1, in0, sel); not (sel_bar, sel); and (y0, in0, sel); and (y1, in1, sel); or (y_out, in0, in1, sel_bar ); endmodule module Mux_4x1 ( output y_out, input in3, in2, in1, in0, sel1, sel0); not (sel_1_bar, sel1); and (s0, sel_1_bar, sel0); and (s1, sel[1], sel0); Mux_2x1 M0 (y_M0, in0, in1, s0); Mux_2x1 M1 (y_M1, in2, in3, s1); or (y_out, y_M0, y_M1 ); endmodule module Mux_8x1 ( output y_out, input in7, in6, in5, in4, in3, in2, in1, in0, sel2, sel1, sel0 ); Mux_4x1 M0 (y_M0, in3, in2, in1, in0, sel1, sel0); Mux_4x1 M1 (y_M1, in7, in6, in5, in4, sl1, sel0); Mux_2x1 M2 (y_out, y_M0, y_M1, sel2); endmodule module Mux_16x1 ( output y_out, Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. input in15, in14, in13, in12, in11, in10, in9, in8, in7, in6, in5, in4, in3, in2, in1, in0, sel3, sel2, sel1, sel0 ); Mux_8x1 M0 (y_M0, in7, in6, in5, in4, in3, in2, in1, in0, sel2, sel1, sel0); Mux_8x1 M1 (y_M1, in15, in14, in13, in12, in11, in10, in9, in8, sel2, sel1, sel0); Mux_2x1 M2 (y_out, y_M0, y_M1, sel3); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 115 116 CHAPTER 5 5.1 (a) R = D'C D Q CP C Q' S = DC (b) R = (D + C')' =D' C D Q C Q' s = (D' + C')' =D C (c) S = (DC)' =D' + C' D CP Q C Q' R = ((DC)' C)' =DC + C' = (D + C') = (D'C)' Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 117 5.2 J 0 2x1 mux D = JQ' + K'Q Q Y K D s 5.3 Q 1 C Q'(t + 1) = (JQ' + K'Q)' = (J' + Q)(K + Q') = J'Q' + KQ J 00 m0 0 J K KQ m4 1 0 1 01 m1 m5 11 m3 1 m7 1 10 m2 0 m6 0 0 1 Q 5.4 (a) P N Q(t + 1) 0 0 1 1 0 1 0 1 0 Q(t) Q'(t) 1 (b) P N Q(t) Q(t + 1) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 1 0 1 1 N NQ P 00 0 P 1 m0 m4 1 01 11 m1 m3 m5 m7 1 1 10 m2 m6 1 Q Q(t+1) = PQ' + NQ (c) Q(t) Q(t+1) P N 0 0 1 1 0 1 0 1 0 1 x x x x 0 1 (d) Connect P and N together. 5.5 The truth table describes a combinational circuit. The state table describes a sequential circuit. The characteristic table describes the operation of a flip-flop. The excitation table gives the values of flip-flop inputs for a given state transition. The four equations correspond to the algebraic expression of the four tables. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 118 5.6 x y xy' + xA D Q D Q A, z C B CP (b) (c) A(t+1) = xy' + xB B(t+1) = xA + xB' z=A 00, 01 x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Next state A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Inputs Present state 00, 01 A 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 z 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 00 0 01 0 11 10 00, 01 10,11 00, 01 10 1 11 1 10, 11 10, 11 y 0 1 0 1 0 1 0 1 Output x 0 0 1 1 0 0 1 1 Next state Q 0 0 0 0 1 1 1 1 Inputs Present state 5.7 Q 0 0 0 1 0 1 1 1 S 0 1 1 0 1 0 0 1 00/0 01/0 10/1 01/0 10/0 11/1 11/0 0 1 00/1 S=x⊕y⊕Q Q(t + 1) = xy + xQ + yQ Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. A counter with a repeated sequence of 00, 01, 10. Present state Next state 5.8 119 A B A B FF Inputs TA TB 0 0 1 1 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 00 01 11 10 1 1 0 1 TA = A + B TB = A' + B Repeated sequence: 01 10 00 5.9 JA = x JB = x 0 KA = B KB = A' 0 00 01 A(t+1) = JAA' + KA'A = xA' + B'A B(t+1) = JBB' + KB'B = xB' + AB x 0 0 0 0 1 1 1 1 A 0 0 1 1 0 0 1 1 B xA' + B'A xB' + AB 0 0 0 1 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 1 0 1 1 1 0,1 11 0 1 10 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 5.10 120 (a) JA = Bx + B'y' KA = B'xy' JB = A'x KB = A + xy' z = Axy + Bx'y' (c) Present state Inputs Next state Output (b) A B x y A B z FF Inputs JA KA JA JB 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 0 0 1 1 1 1 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 AB xy x 00 m0 01 11 m3 m2 m4 m5 m7 m6 m12 m13 m15 1 1 01 1 11 A 10 m1 00 1 m8 1 m9 10 1 1 m14 1 m11 1 B 1 m10 1 y A(t+1) = Ax' + Bx + Ay + A'B'y' AB xy x 00 m0 01 m1 11 m3 00 10 m2 1 m4 A 01 m5 1 m7 1 1 m6 1 m12 m13 m15 m14 m8 m9 m11 m10 B 11 10 y B(t+1) = A'B'x + A'B'(x' + y) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 121 5.11 (a) Present state: Input: Output: Next state: 00 00 01 00 01 11 00 01 11 10 00 01 11 10 10 0 1 0 1 1 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 1 00 01 00 01 11 00 01 11 10 00 01 11 10 10 00 (b) State labels: a: 00, b: 10, c: 11, d: 01 c is equivalent to b d is equivalent to c 0/0 a 1/0 0/1 b 1/0 5.12 (c) input 0 1 0 1 State machine: D-‐flop with direct input of the input to the original machine; output logic: y = (!input) && (state == b) Present state a b d f g state 0 0 1 1 next st 0 1 0 1 Next state 0 1 f b d a g a f b g d output 0 0 0 1 Output 0 1 0 0 0 0 1 0 1 1 0 1 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 5.13 122 (a) State: Input: Output: a 0 0 a 0 0 (b) State: Input: Output: f b c e d g h g g h a 1 1 1 0 0 1 0 0 1 1 1 0 0 0 1 1 1 0 1 0 f b a b d g d g g d a 1 1 1 0 0 1 0 0 1 1 1 0 0 0 1 1 1 0 1 0 5.14 Next state x=0 x=1 Present state ABCDE a b c d e 5.15 00001 00010 00100 01000 10000 00001 00100 00001 10000 00001 00010 01000 01000 01000 01000 Output x=1 x=0 0 0 0 0 0 0 0 0 1 1 DQ = Qʹ′J + QKʹ′ Present state Q 0 0 0 0 1 1 1 1 Inputs J K 0 0 1 1 0 0 1 1 Next state Q 0 1 0 1 0 1 0 1 0 0 1 1 1 0 1 0 Q No change Reset to 0 Set to 1 Complement No change Reset to 0 Set to 1 Complement 1 m4 1 11 m1 m3 m5 m7 1 10 m2 m6 1 1 Q(t+1) = DQ + Q'J + QK' D K m0 01 K J 5.16 00 0 Q J JK clk Q Q Q' Q' (a) DA = Axʹ′ + Bx DB = Aʹ′x + Bxʹ′ Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 123 Present state A B 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Input x 0 1 0 1 0 1 0 1 Next state A B 0 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 A 00 0 A B Bx 1 01 11 m0 m1 m3 m4 m5 m7 1 10 m2 1 m6 1 1 x DA = Ax' + Bx A 00 0 A B Bx 1 01 m0 m1 m4 m5 1 11 m3 10 m2 1 m7 m6 1 1 x DB = A'x + Bx' (b) DA = A'x + Ax' DB = AB + Bx' Present state A B 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Input x 0 1 0 1 0 1 0 1 Next state A B 0 1 0 1 1 0 1 0 0 1 1 0 0 0 1 1 A 00 0 A B Bx 1 01 m0 m1 m4 m5 1 1 11 m3 10 m2 1 m7 m6 1 x DA = A'x + Ax' A 00 0 A B Bx 1 01 m0 m1 m4 m5 1 11 10 m3 m2 m7 m6 1 1 1 x DB = AB + Bx' 5.17 The output is 0 for all 0 inputs until the first 1 occurs, at which time the output is 1. Thereafter, the output is the complement of the input. The state diagram has two states. In state 0: output = input; in state 1: output = input'. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 124 D x Q y Present state Input Next state Output clk A 0 0 1 1 x 0 1 0 1 A 0 1 1 1 y 0 1 1 0 reset_b 0/0 0/1 1/0 reset_b 0 1 1/1 DA = A + x y = Ax' + A'x 5.18 Binary up-down counter with enable E. Present Next state Input state AB x AB 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 01 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 00 11 01 01 01 01 10 10 10 01 11 11 11 11 11 Flip-flop inputs JA KA JB KB 0 x 0 x 1 x 0 x 0 x 0 x 0 x 1 x x 0 x 0 x 1 x 0 x 0 x 0 1 0 x1 0 0 1 1 x x x x 1 1 x x x x x x x x x x 0 0 1 1 0 0 1 1 0 0 1 1 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 125 AB Ex E 00 00 01 11 A 10 01 11 10 m0 m1 m3 m2 m4 m5 m7 m6 m12 m13 m15 x m8 x x m9 x 1 AB 1 Cx 00 01 m14 x B x m11 m10 x 11 A x C 00 10 m0 m4 x x Ex 00 01 11 A 10 m0 m4 x 01 m1 m5 x 11 m3 m7 1 x 10 m2 m6 01 m14 m8 m9 m11 m10 1 E x 11 A 1 x JB = E 5.19 x m7 10 m2 x x m6 x m13 m15 m14 m8 m9 m11 m10 1 B 1 E 00 x m15 x x Ex 00 m13 x AB 1 m12 x m5 m3 x KA = (Bx + B'x')E E 00 m1 11 m12 x JA = (Bx + B'x')E AB 01 10 m0 x 01 m1 x 11 m3 x 10 m2 m4 m5 m7 m12 m13 m15 m14 m8 m9 m11 m10 x x 1 1 x KB = E (a) Unused states (see Fig. P5.19): 101, 110, 111. x m6 x 1 E 1 x Present Next Input Output state state y ABC x ABC 000 0 011 0 000 1 100 1 001 0 001 0 001 1 100 1 010 0 010 0 010 1 000 1 011 0 001 0 011 1 010 1 100 0 010 0 100 1 011 1 d(A, B, C, x) = Σ (10, 11, 12, 13, 14, 15) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 126 AB Cx C 00 00 01 11 A 10 01 m0 m1 m4 m5 1 11 m3 10 AB Cx 1 00 m7 m6 01 m12 x m8 m13 x m9 m15 m14 x B x m11 m10 x 11 A x C 00 m2 10 m0 m4 1 1 00 01 11 A 10 m0 1 m4 01 11 10 m1 m3 m2 m5 m7 m6 01 m14 m8 m9 m11 m10 1 x m7 10 m2 m6 1 m15 m14 m8 m9 m11 m10 1 x x 1 B x x x B x 11 A x C 00 1 m15 x m5 Cx 00 m13 x AB 1 m12 x m3 x DB = A + C'x' + BCx C 00 m1 m13 x x Cx 11 m12 DA = A'B'x AB 01 10 01 m0 m1 m4 m5 11 m3 1 m7 1 1 1 10 m2 m6 m12 m13 m15 m14 m8 m9 m11 m10 x x DC = Cx'+ Ax +A'B'x' x x x x y = A'x B x x The machine is self-correcting, i.e., the unused states transition to known states. 111 101 0/0 1/0 0/0 1/0 011 110 0/0 1/0 010 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 127 (b) With JK flip=flops, the state table is the same as in (a). Flip-flop inputs JA KA JB KB JC KC 0 1 0 1 0 0 0 0 x x x x x x x x x x 1 1 1 0 0 0 x x x x 1 1 x x x x 0 1 1 0 x x 1 0 x x 0 0 x x 0 1 x x 0 1 x x 0 1 x x JA = B'x KA = 1 JB = A + C'x' KB = C' x+ Cx' JC = Ax + A'B'x' KC = x y = A'x The machine is self-correcting because KA = 1. 5.20 From state table 5.4: TA (A, B, x) = Σ (2, 3, 6), TB(A, B, x) = Σ (0, 3, 4, 6). A 00 0 A B Bx 1 01 11 m0 m1 m3 m4 m5 m7 1 A 10 m2 m6 1 00 0 1 A B Bx 1 m0 m4 x TA = A'B + Bx' 5.21 1 1 01 11 m1 m3 m5 m7 1 10 m2 m6 1 x TB = B'x' + A'x + A'Bx The statements associated with an initial keyword execute once, in sequence, with the activity expiring after the last statment competes execution; the statements assocated with the always keyword execute repeatedly, subject to timing control (e.g, #10). 5.22 (a) (b) 0 5.23 20 40 60 80 100 120 140 t 160 (a) RegA = 125, RegB = 125 (b) RegA = 125, RegB = 50 Note: Text has error, with RegB = 30 at page 526). Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 128 5.24 (a) module DFF (output reg Q, input D, clk, preset, clear); always @ (posedge clk, negedge preset, negedge clear ) if (preset == 0) Q <= 1'b1; else if (clear == 0) Q <= 1'b0; else Q <= D; endmodule module t_DFF (); wire Q; reg clk, preset, clear; reg D; DFF M0 (Q, D, clk, preset, clear); initial #160 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork #10 preset = 0; #20 preset = 1; #50 clear = 0; #80 clear = 1; #10 D = 1; #100 D = 0; #200 D = 1; join endmodule Name 0 60 120 clk preset clear D Q (b) module DFF (output reg Q, input D, clk, preset, clear); always @ (posedge clk) if (preset == 0) Q <= 1'b1; else if (clear == 0) Q <= 1'b0; else Q <= D; endmodule Name 0 60 120 clk preset clear D Q Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 129 5.25 module Quad_Input_DFF (output reg Q, input D1, D2, D3, D4, s1, s0, clk, reset_b); always @ (posedge clk, negedge reset_b) if (reset_b == 1'b0) Q <= 0; else case ({s1, s0}) 2'b00: Q <= D1; 2'b01: Q <= D2; 2'b10: Q <= D3; 2'b11: Q <= D4; endcase endmodule module t_Quad_Input_DFF (); wire Q; reg D1, D2, D3, D4, s1, s0, clk, reset_b; Quad_Input_DFF M0 (Q, D1, D2, D3, D4, s1, s0, clk, reset_b); initial #350 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork begin s1 = 0; s0 = 0; end #40 begin s1 = 0; s0 = 1; end #80 begin s1 =1; s0 = 0; end #120 begin s1 = 1; s0 = 0; end #160 begin s1 = 1; s0 = 1; end join initial fork begin D1 = 0; forever #10 D1 = ~D1; end begin D2 = 1; forever #20 D2 = ~D2; end begin D3 = 0; forever #10 D3 = ~D3; end begin D4 = 0; forever #20 D4 = ~D4; end join initial fork #2 reset_b = 1; #3 reset_b = 0; #4 reset_b = 1; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 130 5.26 (a) Q(t + 1) = JQʹ′ + Kʹ′Q When Q = 0, Q(t + 1) = J When Q = 1, Q(t + 1) = Kʹ′ module JK_Behavior_a (output reg Q, input J, K, CLK, reset_b); always @ (posedge CLK, negedge reset_b) if (reset_b == 0) Q <= 0; else if (Q == 0) Q <= J; else Q <= ~K; endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 131 (b) module JK_Behavior_b (output reg Q, input J, K, CLK, reset_b); always @ (posedge CLK, negedge reset_b) if (reset_b == 0) Q <= 0; else case ({J, K}) 2'b00: Q <= Q; 2'b01: Q <= 0; 2'b10: Q <= 1; 2'b11: Q <= ~Q; endcase endmodule module t_Prob_5_26 (); wire Q_a, Q_b; reg J, K, clk, reset_b; JK_Behavior_a M0 (Q_a, J, K, clk, reset_b); JK_Behavior_b M1 (Q_b, J, K, clk, reset_b); initial #100 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork #2 reset_b = 1; #3 reset_b = 0; // Initialize to s0 #4 reset_b = 1; J =0; K = 0; #20 begin J= 1; K = 0; end #30 begin J = 1; K = 1; end #40 begin J = 0; K = 1; end #50 begin J = 1; K = 1; end join endmodule Name 0 40 80 clk reset_b J K Q_a Q_b 5.27 // Mealy FSM zero detector (See Fig. 5.16) module Mealy_Zero_Detector ( output reg y_out, input x_in, clock, reset ); reg [1: 0] state, next_state; parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; always @ (posedge clock, negedge reset) // state transition if (reset == 0) state <= S0; else state <= next_state; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 132 always @ (state, x_in) // Form the next state case (state) S0: begin y_out = 0; if (x_in) next_state = S1; else next_state = S0; end S1: begin y_out = ~x_in; if (x_in) next_state = S3; else next_state = S0; end S2: begin y_out = ~x_in; if (~x_in) next_state = S0; else next_state = S2; end S3: begin y_out = ~x_in; if (x_in) next_state = S2; else next_state = S0; end endcase endmodule module t_Mealy_Zero_Detector; wire t_y_out; reg t_x_in, t_clock, t_reset; Mealy_Zero_Detector M0 (t_y_out, t_x_in, t_clock, t_reset); initial #200 $finish; initial begin t_clock = 0; forever #5 t_clock = ~t_clock; end initial fork t_reset = 0; #2 t_reset = 1; #87 t_reset = 0; #89 t_reset = 1; #10 t_x_in = 1; #30 t_x_in = 0; #40 t_x_in = 1; #50 t_x_in = 0; #52 t_x_in = 1; #54 t_x_in = 0; #70 t_x_in = 1; #80 t_x_in = 1; #70 t_x_in = 0; #90 t_x_in = 1; #100 t_x_in = 0; #120 t_x_in = 1; #160 t_x_in = 0; #170 t_x_in = 1; join endmodule Note: Simulation results match Fig. 5.22. Name 6 46 86 126 166 t_clock t_reset state[1:0] 0 1 3 0 1 0 0 1 0 1 3 2 0 1 t_x_in t_y_out Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 5.28 133 (a) module Prob_5_28a (output A, input x, y, clk, reset_b); parameter s0 = 0, s1 = 1; reg state, next_state; assign A = state; always @ (posedge clk, negedge reset_b) if (reset_b == 0) state <= s0; else state <= next_state; always @ (state, x, y) begin next_state = s0; case (state) s0: case ({x, y}) 2'b00, 2'b11: next_state = s0; 2'b01, 2'b10: next_state = s1; endcase s1: case ({x, y}) 2'b00, 2'b11: next_state = s1; 2'b01, 2'b10: next_state = s0; endcase endcase end endmodule module t_Prob_5_28a (); wire A; reg x, y, clk, reset_b; Prob_5_28a M0 (A, x, y, clk, reset_b); initial #350 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork #2 reset_b = 1; #3 reset_b = 0; // Initialize to s0 #4 reset_b = 1; x =0; y = 0; #20 begin x= 1; y = 1; end #30 begin x = 0; y = 0; end #40 begin x = 1; y = 0; end #50 begin x = 0; y = 0; end #60 begin x = 1; y = 1; end #70 begin x = 1; y = 0; end #80 begin x = 0; y = 1; end join endmodule 0 Name 80 clk reset_b x y A Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 160 134 (b) module Prob_5_28b (output A, input x, y, Clock, reset_b); xor (w1, x, y); xor (w2, w1, A); DFF M0 (A, w2, Clock, reset_b); endmodule module DFF (output reg Q, input D, Clock, reset_b); always @ (posedge Clock, negedge reset_b) if (reset_b == 0) Q <= 0; else Q <= D; endmodule module t_Prob_5_28b (); wire A; reg x, y, clk, reset_b; Prob_5_28b M0 (A, x, y, clk, reset_b); initial #350 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork #2 reset_b = 1; #3 reset_b = 0; // Initialize to s0 #4 reset_b = 1; x =0; y = 0; #20 begin x= 1; y = 1; end #30 begin x = 0; y = 0; end #40 begin x = 1; y = 0; end #50 begin x = 0; y = 0; end #60 begin x = 1; y = 1; end #70 begin x = 1; y = 0; end #80 begin x = 0; y = 1; end join endmodule Name 0 60 120 180 Clock reset_b x y A Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 135 (c) See results of (b) and (c). module t_Prob_5_28c (); wire A_a, A_b; reg x, y, clk, reset_b; Prob_5_28a M0 (A_a, x, y, clk, reset_b); Prob_5_28b M1 (A_b, x, y, clk, reset_b); initial #350 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork #2 reset_b = 1; #3 reset_b = 0; // Initialize to s0 #4 reset_b = 1; x =0; y = 0; #20 begin x= 1; y = 1; end #30 begin x = 0; y = 0; end #40 begin x = 1; y = 0; end #50 begin x = 0; y = 0; end #60 begin x = 1; y = 1; end #70 begin x = 1; y = 0; end #80 begin x = 0; y = 1; end join endmodule Name 0 60 120 180 clk reset_b x y A_a A_b 5.29 module Prob_5_29 (output reg y_out, input x_in, clock, reset_b); parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100; reg [2: 0] state, next_state; always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= s0; else state <= next_state; always @ (state, x_in) begin y_out = 0; next_state = s0; case (state) s0: if (x_in) begin next_state = s4; y_out = 1; end else begin next_state = s3; y_out = 0; end s1: if (x_in) begin next_state = s4; y_out = 1; end else begin next_state = s1; y_out = 0; end s2: if (x_in) begin next_state = s0; y_out = 1; end else begin next_state = s2; y_out = 0; end s3: if (x_in) begin next_state = s2; y_out = 1; end else begin next_state = s1; y_out = 0; end s4: if (x_in) begin next_state = s3; y_out = 0; end else begin next_state = s2; y_out = 0; end default: next_state = 3'bxxx; endcase end endmodule module t_Prob_5_29 (); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 136 wire y_out; reg x_in, clk, reset_b; Prob_5_29 M0 (y_out, x_in, clk, reset_b); initial #350$finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork #2 reset_b = 1; #3 reset_b = 0; // Initialize to s0 #4 reset_b = 1; // Trace the state diagram and monitor y_out x_in = 0; // Drive from s0 to s3 to S1 and park #40 x_in = 1; // Drive to s4 to s3 to s2 to s0 to s4 and loop #90 x_in = 0; // Drive from s0 to s3 to s2 and part #110 x_in = 1; // Drive s0 to s4 etc join endmodule 0 40 80 Name 120 clk reset_b x_in state[2:0] 3 1 4 3 2 0 4 2 0 y_out Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 4 137 5.30 A D B E CLK D Q CLK C CLK 5.31 module Seq_Ckt (input A, B, C, CLK, output reg Q); reg E; always @ (posedge CLK) begin Q = E && C; E = A || B; end endmodule Note: The statements must be written in an order than produces the effect of concurrent assignments. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 138 5.32 initial begin enable = 0; A = 1; B = 0; C = 0; D = 1; E = 1; F = 1; #10 A = 0; B = 1; C = 1; #10 A = 1; B = 0; D = 1; E = 0; #10 B = 1; E = 1; F = 0; #10 enable = 1; B = 0; D= 0; F =1; #10 B = 1; #10 B = 0; D = 1; #10 B = 1; end initial fork enable = 0; A = 1; B = 0; C = 0; D = 1; E = 1; F = 1; #10 begin A = 0; B = 1; end #20 begin A = 1; B = 0; D = 1; E = 0; end #30 begin B = 1; E = 1; F = 0; end #40 begin B = 0; D = 0; F = 1; end #50 begin B = 1; end #60 begin B = 0; D = 1; end #70 begin B = 1; end join 5.33 Signal transitions that are caused by input signals that change on the active edge of the clock race with the clock itself to reach the affected flip-flops, and the outcome is indeterminate (unpredictable). Conversely, changes caused by inputs that are synchronized to the inactive edge of the clock reach stability before the active edge, with predictable outputs of the flip-flops that are affected by the inputs. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 5.34 139 Note: Problem statement should refer to Problem 5.2 instead of Fig 5.5. module JK_flop_Prob_5_34 (output Q, input J, K, clk); wire K_bar; D_flop M0 (Q, D, clk); Mux M1 (D, J, K_bar, Q); Inverter M2 (K_bar, K); endmodule module D_flop (output reg Q, input D, clk); always @ (posedge clk) Q <= D; endmodule module Inverter (output y_bar, input y); assign y_bar = ~y; endmodule module Mux (output y, input a, b, select); assign y = select ? a: b; endmodule module t_JK_flop_Prob_5_34 (); wire Q; reg J, K, clock; JK_flop_Prob_5_34 M0 (Q, J, K, clock); initial #500 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork #10 begin J = 0; K = 0; end // toggle Q unknown #20 begin J = 0; K = 1; end // set Q to 0 #30 begin J = 1; K = 0; end // set q to 1 #40 begin J = 1; K = 1; end // no change #60 begin J = 0; K = 0; end // toggle Q join endmodule Name 0 30 60 90 clock J K Q Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 140 5.35 From Problem 5.6: x y xy' + xA D Q D Q A, z C B CP (b) (c) A(t+1) = xy' + xB B(t+1) = xA + xB' z=A 00, 01 x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Next state A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Inputs Present state 00, 01 A 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 z 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 00 0 01 0 11 10 00, 01 10,11 00, 01 10 1 11 1 10, 11 10, 11 module Prob_5_35 (output out_z, input in_x, in, in_y, clk, reset_b); reg [1:0] state, next_state; assign out_z = ((state == 2'b10) || (state == 2'b11)); always @ (posedge clk) if (reset_b == 1'b0) state <= 2'b00; else state <= next_state; always @ (state, in_x, in_y) case (state) 2'b00: if (({in_x, in_y} == 2'b00) || ({in_x, in_y} == 2'b01)) next_state = 2'b00; else if ({in_x, in_y} == 2'b10) next_state = 2'b11; else next_state = 2'b01; 2'b01: if (({in_x, in_y} == 2'b00) || ({in_x, in_y} == 2'b01)) next_state = 2'b00; else if (({in_x, in_y} == 2'b10) || ({in_x, in_y} == 2'b11)) next_state = 2'b10; 2'b10: if (({in_x, in_y} == 2'b00) || ({in_x, in_y} == 2'b01)) next_state = 2'b00; else if (({in_x, in_y} == 2'b10) || ({in_x, in_y} == 2'b11)) next_state = 2'b11; 2'b11: if (({in_x, in_y} == 2'b00) || ({in_x, in_y} == 2'b01)) next_state = 2'b00; else if (({in_x, in_y} == 2'b10) || ({in_x, in_y} == 2'b11)) next_state = 2'b11; endcase endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 141 module t_Prob_5_35 (); wire out_z; reg in_x, in, in_y, clk, reset_b; Prob_5_35 M0 (out_z, in_x, in, in_y, clk, reset_b); initial #250 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork reset_b = 0; #20 reset_b = 1; #50 {in_x, in_y} = 2'b00; #60 {in_x, in_y} = 2'b01; #70 {in_x, in_y} = 2'b11; #90 {in_x, in_y} = 2'b00; #110 {in_x, in_y} = 2'b11; #120 {in_x, in_y} = 2'b01; // Remain in 2'b00 // Remain in 2'b00 // Transition to 2'b01 // Transition to 2'b00 // Transition to 2'b01 // Transition to 2'b00 #130 {in_x, in_y} = 2'b11; #140 {in_x, in_y} = 2'b10; #150 {in_x, in_y} = 2'b00; #160 {in_x, in_y} = 2'b11; // Transition to 2'b01 // Transition to 2'b10 // Transition to 2'b00 // Transition to 2'b01 #170 {in_x, in_y} = 2'b11; #180 {in_x, in_y} = 2'b01; // Transition to 2'b10 // Transition to 2'b00 #190 {in_x, in_y} = 2'b11; #200 {in_x, in_y} = 2'b11; #210 {in_x, in_y} = 2'b11; // Transition to 2'b01 // Transition to 2'b10 // Transition to 2'b11 #220 {in_x, in_y} = 2'b10; #230 {in_x, in_y} = 2'b11; join endmodule // Remain in 2'b11 // Remain in 2'b11 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 5.36 142 Note: See Problem 5.8 (counter with repeated sequence: (A, B) = 00, 01, 10, 00 .... // See Fig. P5.8 module Problem_5_36 (output A, B, input Clock, reset_b); or (T_A, A, B); or (T_B, A_b, B); T_flop M0 (A, A_b, T_A, Clock, reset_b); T_flop M1 (B, B_b, T_B, Clock, reset_b); endmodule module T_flop (output reg Q, output QB, input T, Clock, reset_b); assign QB = ~ Q; always @ (posedge Clock, negedge reset_b) if (reset_b == 0) Q <= 0; else if (T) Q <= ~Q; endmodule module t_Problem_5_36 (); wire A, B; reg Clock, reset_b; Problem_5_36 M0 (A, B, Clock, reset_b); initial #350$finish; initial begin Clock = 0; forever #5 Clock = ~Clock; end initial fork #2 reset_b = 1; #3 reset_b = 0; #4 reset_b = 1; join endmodule Name 0 30 60 90 Clock reset_b A B 5.37 module Problem_5_37_Fig_5_25 (output reg y, input x_in, clock, reset_b); parameter a = 3'b000, b = 3'b001, c = 3'b010, d = 3'b011, e = 3'b100, f = 3'b101, g = 3'b110; reg [2: 0] state, next_state; always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= a; else state <= next_state; always @ (state, x_in) begin y = 0; next_state = a; case (state) a: begin y = 0; if (x_in == 0) next_state = a; else next_state = b; end Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 143 b: begin y = 0; if (x_in == 0) next_state = c; else next_state = d; end c: begin y = 0; if (x_in == 0) next_state = a; else next_state = d; end d: if (x_in == 0) begin y = 0; next_state = e; end else begin y = 1; next_state = f; end e: if (x_in == 0) begin y = 0; next_state = a; end else begin y = 1; next_state = f; end f: if (x_in == 0) begin y = 0; next_state = g; end else begin y = 1; next_state = f; end g: if (x_in == 0) begin y = 0; next_state = a; end else begin y = 1; next_state = f; end default: next_state = a; endcase end endmodule module Problem_5_37_Fig_5_26 (output reg y, input x_in, clock, reset_b); parameter a = 3'b000, b = 3'b001, c = 3'b010, d = 3'b011, e = 3'b100; reg [2: 0] state, next_state; always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= a; else state <= next_state; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 144 always @ (state, x_in) begin y = 0; next_state = a; case (state) a: begin y = 0; if (x_in == 0) next_state = a; else next_state = b; end b: begin y = 0; if (x_in == 0) next_state = c; else next_state = d; end c: begin y = 0; if (x_in == 0) next_state = a; else next_state = d; end d: if (x_in == 0) begin y = 0; next_state = e; end else begin y = 1; next_state = d; end e: if (x_in == 0) begin y = 0; next_state = a; end else begin y = 1; next_state = d; end default: endcase end endmodule next_state = a; module t_Problem_5_37 (); wire y_Fig_5_25, y_Fig_5_26; reg x_in, clock, reset_b; Problem_5_37_Fig_5_25 M0 (y_Fig_5_25, x_in, clock, reset_b); Problem_5_37_Fig_5_26 M1 (y_Fig_5_26, x_in, clock, reset_b); wire [2: 0] state_25 = M0.state; wire [2: 0] state_26 = M1.state; initial #350 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork x_in = 0; #2 reset_b = 1; #3 reset_b = 0; #4 reset_b = 1; #20 x_in = 1; #40 x_in = 0; // abdea, abdea #60 x_in = 1; #100 x_in = 0; // abdf....fga, abd ... dea #120 x_in = 1; #160 x_in = 0; #170 x_in = 1; #200 x_in = 0; // abdf....fgf...fga, abd ...ded...ea #220 x_in = 1; #240 x_in = 0; #250 x_in = 1; // abdef... // abded... join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 145 0 Name 110 220 clock reset_b x_in state_25[2:0] 0 1 3 4 1 3 state_26[2:0] 0 1 3 4 1 5 3 6 0 4 0 3 5 3 5 6 0 1 4 5 3 4 0 1 4 3 y_Fig_5_25 y_Fig_5_26 5.38 (a) module Prob_5_38a (input x_in, clock, reset_b); parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11; reg [1: 0] state, next_state; always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= s0; else state <= next_state; always @ (state, x_in) begin next_state = s0; case (state) s0: if (x_in == 0) next_state = s0; else if (x_in == 1) next_state = s3; s1: if (x_in == 0) next_state = s1; else if (x_in == 1) next_state = s2; s2: if (x_in == 0) next_state = s2; else if (x_in == 1) next_state = s0; s3: if (x_in == 0) next_state = s3; else if (x_in == 1) next_state = s1; default: next_state = s0; endcase end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 146 module t_Prob_5_38a (); reg x_in, clk, reset_b; Prob_5_38a M0 ( x_in, clk, reset_b); initial #350$finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork #2 reset_b = 1; #3 reset_b = 0; // Initialize to s0 #4 reset_b = 1; #2 x_in = 0; #20 x_in = 1; #60 x_in = 0; #80 x_in = 1; #90 x_in = 0; #110 x_in = 1; #120 x_in = 0; #140 x_in = 1; #150 x_in = 0; #170 x_in= 1; join endmodule 0 Name 60 120 180 clk reset_b x_in state[1:0] 0 3 1 2 0 3 1 2 (b) module Prob_5_38b (input x_in, clock, reset_b); parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11; reg [1: 0] state, next_state; always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= s0; else state <= next_state; always @ (state, x_in) begin next_state = s0; case (state) s0: if (x_in == 0) next_state = s0; else if (x_in == 1) next_state = s3; s1: if (x_in == 0) next_state = s1; else if (x_in == 1) next_state = s2; s2: if (x_in == 0) next_state = s2; else if (x_in == 1) next_state = s0; s3: if (x_in == 0) next_state = s3; else if (x_in == 1) next_state = s1; default: next_state = s0; endcase end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 0 3 147 module t_Prob_5_38b (); reg x_in, clk, reset_b; Prob_5_38b M0 ( x_in, clk, reset_b); initial #350$finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork #2 reset_b = 1; #3 reset_b = 0; // Initialize to s0 #4 reset_b = 1; #2 x_in = 0; #20 x_in = 1; #60 x_in = 0; #80 x_in = 1; #90 x_in = 0; #110 x_in = 1; #120 x_in = 0; #140 x_in = 1; #150 x_in = 0; #170 x_in= 1; join endmodule Name 0 60 120 180 clk reset_b x_in state[1:0] 0 3 1 2 0 3 1 2 0 3 1 5.39 module Serial_2s_Comp (output reg B_out, input B_in, clk, reset_b); // See problem 5.17 parameter S_0 = 1'b0, S_1 = 1'b1; reg state, next_state; always @ (posedge clk, negedge reset_b) begin if (reset_b == 0) state <= S_0; else state <= next_state; end always @ (state, B_in) begin B_out = 0; case (state) S_0: if (B_in == 0) begin next_state = S_0; B_out = 0; end else if (B_in == 1) begin next_state = S_1; B_out = 1; end S_1: begin next_state = S_1; B_out = ~B_in; end default: next_state = S_0; endcase end endmodule module t_Serial_2s_Comp (); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 2 0 148 wire B_in, B_out; reg clk, reset_b; reg [15: 0] data; assign B_in = data[0]; always @ (negedge clk, negedge reset_b) if (reset_b == 0) data <= 16'ha5ac; else data <= data >> 1; // Sample bit stream Serial_2s_Comp M0 (B_out, B_in, clk, reset_b); initial #150 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork #10 reset_b = 0; #12 reset_b = 1; join endmodule Name 0 60 120 clk reset_b B_in state B_out 5.40 EF = 0x s0 10 0x 10 11 11 11 11 s3 s1 10 0x 10 s2 0x module Prob_5_40 (input E, F, clock, reset_b); parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11; reg [1: 0] state, next_state; always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= s0; else state <= next_state; always @ (state, E, F) begin Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 149 next_state = s0; case (state) s0: if (E == 0) next_state = s0; else if (F == 1) next_state = s1; else next_state = s3; s1: if (E == 0) next_state = s1; else if (F == 1) next_state = s2; else next_state = s0; s2: if (E == 0) next_state = s2; else if (F == 1) next_state = s3; else next_state = s1; s3: if (E == 0) next_state = s3; else if (F == 1) next_state = s0; else next_state = s2; default: next_state = s0; endcase end endmodule module t_Prob_5_40 (); reg E, F, clk, reset_b; Prob_5_40 M0 ( E, F, clk, reset_b); initial #350$finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork #2 reset_b = 1; #3 reset_b = 0; // Initialize to s0 #4 reset_b = 1; #2 E = 0; #20 begin E = 1; F = 1; end #60 E = 0; #80 E = 1; #90 E = 0; #110 E = 1; #120 E = 0; #140 E = 1; #150 E = 0; #170 E= 1; #170 F = 0; join endmodule Name 0 100 200 clk reset_b E F state[1:0] 0 1 2 3 0 1 2 3 2 1 0 3 2 1 5.41 module Prob_5_41 (output reg y_out, input x_in, clock, reset_b); parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100; reg [2: 0] state, next_state; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 150 always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= s0; else state <= next_state; always @ (state, x_in) begin y_out = 0; next_state = s0; case (state) s0: if (x_in) begin next_state = s4; y_out = 1; end else begin next_state = s3; y_out = 0; end s1: if (x_in) begin next_state = s4; y_out = 1; end else begin next_state = s1; y_out = 0; end s2: if (x_in) begin next_state = s0; y_out = 1; end else begin next_state = s2; y_out = 0; end s3: if (x_in) begin next_state = s2; y_out = 1; end else begin next_state = s1; y_out = 0; end s4: if (x_in) begin next_state = s3; y_out = 0; end else begin next_state = s2; y_out = 0; end default: next_state = 3'bxxx; endcase end endmodule module t_Prob_5_41 (); wire y_out; reg x_in, clk, reset_b; Prob_5_41 M0 (y_out, x_in, clk, reset_b); initial #350$finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork #2 reset_b = 1; #3 reset_b = 0; // Initialize to s0 #4 reset_b = 1; // Trace the state diagram and monitor y_out x_in = 0; // Drive from s0 to s3 to S1 and park #40 x_in = 1; // Drive to s4 to s3 to s2 to s0 to s4 and loop #90 x_in = 0; // Drive from s0 to s3 to s2 and part #110 x_in = 1; // Drive s0 to s4 etc join endmodule 0 40 80 Name 120 clk reset_b x_in state[2:0] 3 1 4 3 2 0 4 2 0 y_out Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 4 151 5.42 module Prob_5_42 (output A, B, B_bar, y, input x, clk, reset_b); // See Fig. 5.29 wire w1, w2, w3, D1, D2; and (w1, A, x); and (w2, B, x); or (D_A, w1, w2); and (w3, B_bar, x); and (y, A, B); or (D_B, w1, w3); DFF M0_A (A, D_A, clk, reset_b); DFF M0_B (B, D_B, clk, reset_b); not (B_bar, B); endmodule module DFF (output reg Q, input data, clk, reset_b); always @ (posedge clk, negedge reset_b) if (reset_b == 0) Q <= 0; else Q <= data; endmodule module t_Prob_5_42 (); wire A, B, B_bar, y; reg bit_in, clk, reset_b; wire [1:0] state; assign state = {A, B}; wire detect = y; Prob_5_42 M0 (A, B, B_bar, y, bit_in, clk, reset_b); // Patterns from Problem 5.45. initial #350$finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork #2 reset_b = 1; #3 reset_b = 0; #4reset_b = 1; // Trace the state diagram and monitor detect (assert in S3) bit_in = 0; // Park in S0 #20 bit_in = 1; // Drive to S0 #30 bit_in = 0; // Drive to S1 and back to S0 (2 clocks) #50 bit_in = 1; #70 bit_in = 0; // Drive to S2 and back to S0 (3 clocks) #80 bit_in = 1; #130 bit_in = 0;// Drive to S3, park, then and back to S0 join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 152 0 Name 50 100 150 reset_b clk A B B_bar y state[1:0] x 0 1 0 1 2 0 1 2 3 0 detect 5.43 module Binary_Counter_3_bit (output [2: 0] count, input clk, reset_b) always @ (posedge clk) if (reset_b == 0) count <= 0; else count <= next_count; always @ (count) begin case (state) 3'b000: count = 3'b001; 3'b001: count = 3'b010; 3'b010: count = 3'b011; 3'b011: count = 3'b100; 3'b100: count = 3'b001; 3'b101: count = 3'b010; 3'b110: count = 3'b011; 3'b111: count = 3'b100; default: count = 3'b000; endcase end endmodule module t_Binary_Counter_3_bit () wire [2: 0] count; reg clk, reset_b; Binary_Counter_3_bit M0 ( count, clk, reset_b) initial #150 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork reset = 1; #10 reset = 0; #12 reset = 1; endmodule Name 0 50 100 150 reset_b clk count[2:0] x 0 1 2 3 4 5 6 7 0 1 2 3 4 5 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 6 153 Alternative: structural model. module Prob_5_41 (output A2, A1, A0, input T, clk, reset_bar); wire toggle_A2; T_flop M0 (A0, T, clk, reset_bar); T_flop M1 (A1, A0, clk, reset_bar); T_flop M2 (A2, toggle_A2, clk, reset_bar); and (toggle_A2, A0, A1); endmodule module T_flop (output reg Q, input T, clk, reset_bar); always @ (posedge clk, negedge reset_bar) if (!reset_bar) Q <= 0; else if (T) Q <= ~Q; else Q <= Q; endmodule module t_Prob_5_41; wire A2, A1, A0; wire [2: 0] count = {A2, A1, A0}; reg T, clk, reset_bar; Prob_5_41 M0 (A2, A1, A0, T, clk, reset_bar); initial #200 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork reset_bar = 0; #2 reset_bar = 1; #40 reset_bar = 0; #42 reset_bar = 1; join initial fork T = 0; #20 T = 1; #70 T = 0; #110 T = 1; join endmodule If the input to A0 is changed to 0 the counter counts incorrectly. It resumes a correct counting sequence when T is changed back to 1. Name 0 40 80 120 160 200 Default clk reset_bar T A2 A1 A0 count[2:0] 0 1 2 0 1 2 3 5 7 1 3 4 5 6 7 0 1 2 3 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 4 154 5.44 module DFF_asynch_reset (output reg Q, input data, clk, reset); always @ (posedge clk, posedge reset) // Asynchronous reset if (reset) Q <= 0; else Q <= data; endmodule module t_DFF_asynch_reset (); reg data, clk, reset; wire Q; DFF_asynch_reset M0 (Q, data, clk, reset); initial #150 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork reset = 0; #7 reset = 1; #41 reset = 0; #82 reset = 1; #97 reset = 0; #12 data = 1; #50 data = 0; #60 data = 1; #80 data = 0; #90 data = 1; #110 data = 0; join endmodule Name 0 50 100 150 reset clk data Q 5.45 module Seq_Detector_Prob_5_45 (output detect, input bit_in, clk, reset_b); parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3; reg [1: 0] state, next_state; assign detect = (state == S3); always @ (posedge clk, negedge reset_b) if (reset_b == 0) state <= S0; else state <= next_state; always @ (state, bit_in) begin next_state = S0; case (state) 0: if (bit_in) next_state = S1; else state = S0; 1: if (bit_in) next_state = S2; else next_state = S0; 2: if (bit_in) next_state = S3; else state = S0; 3: if (bit_in) next_state = S3; else next_state = S0; default: next_state = S0; endcase end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 155 module t_Seq_Detector_Prob_5_45 (); wire detect; reg bit_in, clk, reset_b; Seq_Detector_Prob_5_45 M0 (detect, bit_in, clk, reset_b); initial #350$finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork #2 reset_b = 1; #3 reset_b = 0; #4reset_b = 1; // Trace the state diagram and monitor detect (assert in S3) bit_in = 0; // Park in S0 #20 bit_in = 1; // Drive to S0 #30 bit_in = 0; // Drive to S1 and back to S0 (2 clocks) #50 bit_in = 1; #70 bit_in = 0; // Drive to S2 and back to S0 (3 clocks) #80 bit_in = 1; #130 bit_in = 0; // Drive to S3, park, then and back to S0 join endmodule Name 0 40 80 120 reset_b clk bit_in state[1:0] x 0 1 0 1 2 0 1 2 3 detect Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 0 156 5.46 Pending simulation results Assumption: Synchronous active-low reset Moore machine reset_b, x_in 01, 00, 10 y_out 000 0 11 001 1 010 1 1x 1x 011 1 1x 100 0 1x 101 0 xx 0x 0x 0x 0x Verify that machine remains in state 000 while reset_b is asserted, independently of x_in. Verify that machine makes transition from 000 to 001 if not reset_b and if x_in is asserted. Verify that state transitions from 000 through 101 are correct. Verify reset_b "on the fly." Verify that y_out is asserted correctly. module Prob_5_46 (output y_out, input x_in, clk, reset_b); reg [2:0] state, next_state; assign y_out = (state == 3'b001)||(state == 3'b010) || (state == 3'b011); always @ (posedge clk) if (reset_b == 1'b0) state <= 3'b000; else state <= next_state; always @ (x_in, state) begin next_state = 3'b000; case (state) 3'b000: if (x_in) next_state = 3'b001; else next_state = 3'b000; 3'b001: next_state = 3'b010; 3'b010: next_state = 3'b011; 3'b011: next_state = 3'b100; 3'b100: next_state = 3'b101; 3'b101: next_state = 3'b000; default: next_state = 3'b000; endcase end endmodule module t_Prob_5_46 (); reg x_in, clk, reset_b; wire y_out; Prob_5_46 M0 (y_out, x_in, clk, reset_b); initial #200 $finish; initial begin clk = 0; forever #5 clk = !clk; end initial fork reset_b = 0; #10 reset_b = 1; #80 reset_b = 0; #90 reset_b = 1; x_in = 0; #30 x_in = 1; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 157 #40 x_in = 1; #50 x_in = 0; #60 x_in = 1; #70 x_in = 0; #120 x_in = 1; #130 x_in = 0; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 158 5.47 Assume synchronous active-low reset. module Prob_5_47 (output reg [3:0] y_out, input Run, clk, reset_b); always @ (posedge clk) if (reset_b == 1'b0) y_out <= 4'b000; else if (Run && (y_out < 4'b1110)) y_out <= y_out + 2'b10; else if (Run && (y_out == 4'b1110)) y_out <= 4'b0000; else y_out <= y_out; // redundant statement and may be omitted endmodule // Verify that counting is prevented while reset_b is asserted, independently of Run // Verify that counting is initiated by Run if reset_b is de-asserted // Verify reset on-the-fly // Verify that deasserting Run suspends counting // Verify wrap-around of counter. module t_Prob_5_47 (); reg Run, clk, reset_b; wire [3:0] y_out; Prob_5_47 M0 (y_out, Run, clk, reset_b); initial #300 $finish; initial begin clk = 0; forever #5 clk = !clk; end initial fork reset_b = 0; #30 reset_b = 1; Run = 1; #30 Run = 0; #50 Run = 1; #70 Run = 0; #90 reset_b = 0; #120 reset_b = 1; #150 Run = 1; #180 Run = 0; #200 Run = 1; join endmodule // Attempt to run is overridden by reset_b // Initiate counting // Pause // reset on-the-fly // De-assert reset_b // Resume counting // Pause counting // Resume counting Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 159 5.48 Assume "a" is the reset state. module Prob_5_48 (output reg y_out, input x_in, clk, reset_b); parameter s_a = 2'd0; parameter s_b = 2'd1; parameter s_c = 2'd2; parameter s_d = 2'd3; reg [1: 0] state, next_state; always @ (posedge clk) if (reset_b == 1'b0) state <= s_a; else state <= next_state; always @ (state, x_in) begin next_state = s_a; y_out = 0; case (state) s_a: if (x_in == 1'b0) begin next_state = s_b; y_out = 1; end else begin next_state = s_c; y_out = 0; end s_b: if (x_in == 1'b0) begin next_state = s_c; y_out = 0; end else begin next_state = s_d; y_out = 1; end s_c: if (x_in == 1'b0) begin next_state = s_b; y_out = 0; end else begin next_state = s_d; y_out = 1; end s_d: if (x_in == 1'b0) begin next_state = s_c; y_out = 1; end else begin next_state = s_a; y_out = 0; end default: begin next_state = s_a; y_out = 0; end endcase end endmodule Verify reset action. Verify state transitions. Transition to a; hold x_in = 0 and get loop bc… Transition to a; hold x_in = 1 and get loop acda… Transitons to b; hold x_in = 1 and get loop bdacd… Transition to d; hold x_in = 0 and get loop dcbc… Confirm Mealy outputs at each state/input pair Verify reset on-the-fly. module t_Prob_5_48 (); reg x_in, clk, reset_b; wire y_out; Prob_5_48 M0 (y_out, x_in, clk, reset_b); initial #400 $finish; initial begin clk = 0; forever #5 clk = !clk; end initial fork reset_b = 0; #30 reset_b = 1; #30 x_in = 0; // loop abcbcbc… #100 reset_b = 0; #110 reset_b = 1; #110 x_in = 1; // loop acdacda… #200 reset_b = 0; #210 reset_b = 1; #210 x_in = 0; #220 x_in = 1; // loop bdacdacd… Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 160 #300 reset_b = 0; #310 reset_b = 1; #310 x_in = 1; #330 x_in = 0; join endmodule // loop acdcbcbc…. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 161 5.49 Assume "a" is the reset state. module Prob_5_49 (output reg y_out, input x_in, clk, reset_b); parameter s_a = 2'd0; parameter s_b = 2'd1; parameter s_c = 2'd2; parameter s_ =d 2'd3; reg [1: 0] state, next_state; always @ (posedge clk) if (reset_b == 1'b0) state <= s_a; else state <= next_state; always @ (state, x_in) begin next_state = s_a; y_out = 1'b0; case (state) s_a: if (x_in == 1'b0) next_state = s_b; else next_state = s_c; s_b: begin y_out = 1'b1; if (x_in == 1'b0) next_state = s_c; else next_state = s_d; end s_c: begin y_out = 1'b1; if (x_in == 1'b0) next_state = s_b; else next_state = s_d; end s_d: if (x_in == 1'b0) next_state = s_c; else next_state = s_a; default: next_state = s_a; endcase end endmodule // Verify reset action. // Verify state transitions. // Transition to a; hold x_in = 0 and get loop abcbc… // Transition to a; hold x_in = 1 and get loop acda… // Transitons to b; hold x_in = 1 and get loop bdacd… // Transition to d; hold x_in = 0 and get loop dcbc… // Confirm Moore outputs at each state // Verify reset on-the-fly. module t_Prob_5_49 (); reg x_in, Run, clk, reset_b; wire y_out; Prob_5_49 M0 (y_out, x_in, clk, reset_b); initial #400 $finish; initial begin clk = 0; forever #5 clk = !clk; end initial fork reset_b = 0; #30 reset_b = 1; #30 x_in = 0; // loop abcbcbc… #100 reset_b = 0; #110 reset_b = 1; #110 x_in = 1; // loop acdacda… #200 reset_b = 0; #210 reset_b = 1; #210 x_in = 0; #220 x_in = 1; // loop bdacdacd… Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 162 #300 reset_b = 0; #310 reset_b = 1; #310 x_in = 1; #330 x_in = 0; join endmodule // loop acdcbcbc…. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 163 5.50 The machine is to remain in its initial state until a second sample of the input is detected to be 1. A flag will be set when the first sample is obtained. This will enable the machine to detect the presence of the second sample while being in the initial state. The machine is to assert its output upon detection of the second sample and to continue asserting the output until the fourth sample is detected. Assumption: Synchronous active-low reset Moore machine, links for reset on-the-fly are implicit and not shown Set_flag reset_b && x_in && !flag !reset_b || !x_in a 0 0 reset_b && x_in && flag b 1 0 c 1 Clr_flag Note: the output signal y_out is a Moore-type output. The control signals Set_flag and Clr_flag are not. module Prob_5_50 (output y_out, input x_in, clk, reset_b); parameter s_a = 2'd0; parameter s_b = 2'd1; parameter s_c = 2'd2; reg Set_flag; reg Clr_flag; reg [1:0] state, next_state; assign y_out = (state == s_b) || (state == s_c) ; always @ (posedge clk) if (reset_b == 1'b0) state <= s_a; else state <= next_state; always @ (state, x_in, flag) begin next_state = s_a; Set_flag = 0; Clr_flag = 0; case (state) s_a: if ((x_in == 1'b1) && (flag == 1'b0)) begin next_state = s_a; Set_flag = 1; end else if ((x_in == 1'b1) && (flag == 1'b1)) begin next_state = s_b; Set_flag = 0; end else if (x_in == 1'b0) next_state = s_a; s_b: if (x_in == 1'b0) next_state = s_b; else begin next_state = s_c; Clr_flag = 1; end s_c: if (x_in == 1'b0) next_state = s_c; else next_state = s_a; default: begin next_state = s_a; Clr_flag = 1'b0; Set_flag = 1'b0; end endcase end always @ (posedge clk) if (reset_b == 1'b0) flag <= 0; else if (Set_flag) flag <= 1'b1; else if (Clr_flag) flag <= 1'b0; endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 164 // Verify reset action // Verify detection of first input // Verify wait for second input // Verify transition at detection of second input // Verify with between detection of input // Verify transition to s_d at fourth detection of input // Verify return to s_a and clearing of flag after fourth input // Verify reset on-the-fly module t_Prob_5_50 (); wire y_out; reg x_in, clk, reset_b; Prob_5_50 M0 (y_out, x_in, clk, reset_b); initial #500 $finish; initial begin clk = 0; forever #5 clk = !clk; end initial fork reset_b = 1'b0; #20 reset_b = 1; #20 x_in = 1'b0; #40 x_in = 1'b1; #50 x_in = 1'b0; #80 x_in = 1'b1; #100 x_in = 0; #150 x_in = 1'b1; #160 x_in = 1'b0; #200 x_in = 1'b1; #230 reset_b = 1'b0; #250 reset_b = 1'b1; #300 x_in = 1'b0; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 165 5.51 Assumption: Synchronous active-low reset Moore machine, links for reset on-the-fly are implicit and not shown reset_b 0 0 1 s0 0 0 1 s1 0 0 1 s2 1 s3 1 1 5.52 Assumption: Synchronous active-low reset Moore/Mealy machine, links for reset on-the-fly are implicit and not shown Mealy output reset_b 0 0 0/1 0 1 s0 0 1 s1 0 1/0 s2 s3 1 1 5.53 Assumption: Synchronous active-low reset Moore machine, links for reset on-the-fly are implicit and not shown reset_b 0 0 1 s0 0 0 1 s1 0 0 1 s2 0 s3 1 1 5.54 Assumption: Synchronous active-low reset Moore machine, links for reset on-the-fly are implicit and not shown reset_b s0 0 01, 10 01, 10 s1 0 00, 11 00, 11 01, 10 s2 1 00, 11 5.55 Assumption: Synchronous active-low reset Mealy machine, links for reset on-the-fly are implicit and not shown 0/1 0/0 0/0 reset_b 0/0 s0 1/0 s1 1/0 s2 1/0 s3 1/1 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 166 5.56 reset_b x_in 0 x 0 x 0 x 0 x 0 x 0 x 0 x 0 x D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 nD2 0 0 0 0 0 0 0 0 nD1 0 0 0 0 0 0 0 0 nD0 0 0 0 0 0 0 0 0 1 1 1 0 1 x 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 1 0 1 x 0 0 0 1 1 1 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1 0 1 x 1 1 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1 1 0 1 x 1 1 1 1 1 1 0 0 1 1 0 0 1 0 0 0 0 0 For reset_b = 1: nD2 = (x_in D2'D1D0') || (x_in' D2 D1' D0') || (x_in D2 D1' D0') || (x_in D2 D1 D0') nD1 = (x_in D2' D1' D0') || (x_in' D2' D1 D0') || (x_in D2 D1' D0') || (x_in' D2 D1 D0') Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 167 x_in D2 D1 D0 00 D1 01 11 x_in D2 10 m0 m1 m3 m2 m4 m5 m7 m6 m13 m15 m14 00 00 D1 01 1 m12 11 1 10 m0 m1 m3 m2 m4 m5 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 1 m9 m11 m10 1 01 D2 1 10 1 11 x_in 1 m8 10 1 D0 D0 nD2 = D2 D1'D0' + x_in D1 D0' x_in 11 00 01 x_in D1 D0 D2 D1 D0 nD1 = x_inD1' D0' + x_in' D1 D0' Reset_b Clk D2 D Clr D2' D1 D Clr D1' Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. D2 168 5.57 Assume synchronous active-low reset. Assume that the counter is controlled by assertion of Run. module Prob_5_57 (output reg [2:0] y_out, input Run, clk, reset_b); always @ (posedge clk) if (reset_b == 1'b0) y_out <= 3'b000; else if (Run && (y_out < 3'b110)) y_out <= y_out + 3'b010; else if (Run && (y_out == 3'b110)) y_out <= 3'b000; else y_out <= y_out; // redundant statement and may be omitted endmodule // Verify that counting is prevented while reset_b is asserted, independently of Run // Verify that counting is initiated by Run if reset_b is de-asserted // Verify reset on-the-fly // Verify that deasserting Run suspends counting // Verify wrap-around of counter. module t_Prob_5_57 (); reg Run, clk, reset_b; wire [2:0] y_out; Prob_5_57 M0 (y_out, Run, clk, reset_b); initial #300 $finish; initial begin clk = 0; forever #5 clk = !clk; end initial fork reset_b = 0; #30 reset_b = 1; Run = 1; #30 Run = 0; #50 Run = 1; #70 Run = 0; #90 reset_b = 0; #120 reset_b = 1; #150 Run = 1; #180 Run = 0; #200 Run = 1; join endmodule // Attempt to run is overridden by reset_b // Initiate counting // Pause // reset on-the-fly // De-assert reset_b // Resume counting // Pause counting // Resume counting Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 169 5.58 module Prob_5_58 (output reg y_out, input x_in, clk, reset_b) parameter s0 = 2'b00; parameter s1 = 2'b01; parameter s2= 2'b10; parameter s3 = 2'b11; reg [1:0] state, next_state; always @ (posedge clk, negedge reset_b) if (reset_b == 1'b0) state <= s0; else state <= next_state; always @(state, x_in) begin y_out = 0; next_state = s0; case(state) s0: if (x_in == 1'b0) next_state = s0; else if (x_in = 1'b1) next_state = s1; s1: if (x_in == 1'b0) next_state = s0; else if (x_in = 1'b1) next_state = s2; s2: if (x_in == 1'b0) next_state = s0; else if (x_in = 1'b1) next_state = s3; s3: if (x_in == 1'b0) next_state = s0; else if (x_in = 1'b1) begin next_state = s3; y_out = 1; end default: begin next_state = s0; y_out = 0; end endcase end endmodule module t_Prob_5_58 (); wire y_out; reg x_in, clk, reset_b; Prob_5_58 M0 (y_out, x_in, clk, reset_b) initial begin clk = 0; forever #5 clk = !clk; end initial fork reset_b = 0; x_in = 0; #20 reset_b = 1; #40 reset_b = 1; #50 x_in = 1; #60 x_in = 0; #80 x_in = 1; #90 x+in = 0; #110 x_in = 1; #120 x_in = 1; #150 x_in = 0; #200 x_in = 1; #210 reset_b = 0; #240 reset_b = 1; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 170 5.59 module Prob_5_59 (output reg [2: 0] count, input enable, clk, reset_b); always @ (posedge clk) if (reset_b == 1'b0) count <= 3'b000; else if (enable) case (count) 3'b000: count <= 3'b010; 3'b010: count <= 3'b100; 3'b100: count <= 3'b110; 3'b110: count <= 3'b000; default: count <= 3'b111; // Use for error detection endcase endmodule module t_Prob_5_59 (); wire [2:0] count; reg enable, clk, reset_b; Prob_5_59 M0 (count, enable, clk, reset_b); initial #200 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork reset_b = 0; #10 reset_b = 1; #100 reset_b = 0; #130 reset_b = 1; enable = 0; #30 enable = 1; #60 enable = 0; #90 enable = 1; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 171 5.60 Assume synchronous active-low reset. Assume that counting is controlled by Run. module Prob_5_60 (output reg [3:0] y_out, input Run, clk, reset_b); always @ (posedge clk) if (reset_b == 1'b0) y_out <= 4'b000; else if (Run && (y_out < 4'b1001)) y_out <= y_out + 4'b0001; else if (Run && (y_out == 4'b1001)) y_out <= 4'b0000;500 else y_out <= y_out; // redundant statement and may be omitted endmodule // Verify that counting is prevented while reset_b is asserted, independently of Run // Verify that counting is initiated by Run if reset_b is de-asserted // Verify reset on-the-fly // Verify that deasserting Run suspends counting // Verify wrap-around of counter. module t_Prob_5_60 (); reg Run, clk, reset_b; wire [3:0] y_out; Prob_5_60 M0 (y_out, Run, clk, reset_b); initial #500 $finish; initial begin clk = 0; forever #5 clk = !clk; end initial fork reset_b = 0; #30 reset_b = 1; Run = 1; #30 Run = 0; #50 Run = 1; #70 Run = 0; #90 reset_b = 0; #120 reset_b = 1; #150 Run = 1; #180 Run = 0; #200 Run = 1; join endmodule // Attempt to run is overridden by reset_b // Initiate counting // Pause // reset on-the-fly // De-assert reset_b // Resume counting // Pause counting // Resume counting Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 172 CHAPTER 6 6.1 The structure shown below gates the clock through a nand gate. In practice, the circuit can exhibit two problems if the load signal is asynchronous: (1) the gated clock arrives in the setup interval of the clock of the flip-flop, causing metastability, and (2) the load signal truncates the width of the clock pulse. Additionally, the propagation delay through the nand gate might compromise the synchronicity of the overall circuit. Connect to the clock input of each flip-flop. Load Clock 6.2 Modify Fig. 6.2, with each stage replicating the first stage shown below: load clear D Q A0 I0 clk Load 0 0 1 6.3 Clear 0 1 x D A0 0 I0 Operation No change Clear to 0 Load input Note: In this design, clear has priority over load. Serial data is transferred one bit at a time, in sequence. Parallel data is transferred n bits at a time (n > 1), concurrently. A shift register can convert serial data into parallel data by first shifting one bit a time into the register and then taking the parallel data from the register outputs. A shift register with parallel load can convert parallel data to a serial format by first loading the data in parallel and then shifting the bits one at a time. 6.4 0110 => 0011, 0001, 1000, 1100, 1110, 0111, 1011 6.5 (a) See Fig. 11.19: IC 74194 (b) See Fig. 11.20. Connect two 74194 ICs to form an 8-bit register. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 6.6 173 First stage of register: shift load serial input D I0 A0 Q clk 6.7 First stage of register: Select S1 S0 0 1 2 3 0 Ii 4x1 Mux Y D Ai Q A'i Q' clk 6.8 A = 0010, 0001, 1000, 1100. Carry = 1, 1, 1, 0 6.9 (a) In Fig. 6.5, complement the serial output of shift register B (with an inverter), and set the initial value of the carry to 1. (b) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 0 0 1 0 1 0 0 x x x x x x x x 0 0 1 0 x xy Present Next FF state Inputs state Output inputs Q x y Q D JQ KQ Q 00 0 Q 1 m0 m4 01 m1 m5 x 11 10 m3 1 m7 x m2 m6 x x y JQ = x'y x xy Q 00 0 Q 1 m0 m4 x 01 m1 11 m3 x m5 x m7 10 m2 m6 x 1 x KQ = xy' D= Q x y Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 6.10 174 See solution to Problem 5.7. Note that y = x if Q = 0, and y = x' if Q = 1. Q is set on the first 1 from x. Note that x ⊕ 0 = x, and x ⊕ 1 = x'. Serial output Shift Register Serial input D From shift control y x Q Q R clk Reset to 0 initially 6.11 (a) A count down counter. (b) A count up counter. 6.12 Similar to diagram of Fig. 6.8. (a) With the bubbles in C removed (positive-edge). (b) With complemented flip-flops connected to C. 6.13 A1 4-Bit Ripple Counter Clear Asynchronous, active-low) 6.14 A2 0 1 0 A3 1 A4 (a) 10_0110_0111 -> 10_011_1000 4; (b) 11_1100_0111 -> 11_1100_1000 4; (c) 00_0000_1111 -> 00_0001_0000 5 6.15 The worst case is when all 10 flip-flops are complemented. The maximum delay is 10 x 3ns = 30 ns. The maximum frequency is 109/30 = 33.3 MHz Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 6.16 6.17 6.18 175 Q8 Q4 Q2 Q1 : Next state: Next state: 1010 1011 0100 1100 1101 0100 1110 Self correcting 1111 0000 1010 → 1011 → 0100 1100 → 1101 → 0100 1110 → 1111 → 0000 With E denoting the count enable in Fig. 6.12 and D-flip-flops replacing the J-K flip-flops, the toggling action of the bits of the counter is determined by: T0 = E, T1 = A0E, T2 = A0A1E, T3 = A0A1A2E. Since DA = A ⊕ TA the inputs of the flip-flops of the counter are determined by: DA0 = A0⊕E; DA1 = A1⊕(A0E); DA2 = A2⊕(A0A1E); DA3 = A3⊕(A0A1A2E). When up = down = 1 the circuit counts up. up x Combinational Circuit down y up down x y Operation 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 0 No change Count down Count up No change Add this to Fig. 6.13 up down 6.19 x x = up (down)' y = (up)'down y (b) From the state table in Table 6.5: DQ1 = Q'1 DQ2 = ∑ (1, 2, 5, 6) DQ4 = ∑ (3, 4, 5, 6) DQ8 = ∑ (7, 8) Don't care: d = ∑ (10, 11, 12, 13, 14, 15) Simplifying with maps: DQ2 = Q2Q'1 + Q'8Q'2Q1 DQ4 = Q4Q'1 + Q4Q'2 + Q'4Q2Q1 DQ8 = Q8Q'1 + Q4Q2Q1 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 176 (a) Present state Next state Flip-flop inputs A8 A4 A2 A1 A8 A4 A2 A1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 JA8 KA8 JA4 KA4 JA2 KA2 JA1 KA1 0 0 0 0 0 0 0 1 x x 0 0 0 1 x x x x 0 0 0 1 x x 0 1 x x 0 0 1 x 1 x 1 x 1 x 1 x x x x x x x x x 0 1 x x x x 0 0 0 1 x x x x 0 1 x x 0 1 x x x 1 x 1 x 1 x 1 x 1 JA1 = 1 KA1 = 1 JA2 = A1A'8 KA2 = A1 JA4 = A1A2 KA4 = A1A2 JA8 = A1A2A4 KA8 = A1 d(A8, A4, A2, A1) = Σ (10, 11, 12, 13, 14, 15) (b) A_count[1] A_count[0] Count Load CLK Clear Data_in[0] Data_in[3] Fig. 6.14 Data_in[1] C_out 16-bit counter needs 4 circuits with output carry connected to the count input of the next stage. Data_in[2] Block diagram of 4-bit circuit: A_count[2] (a) A_count[3] 6.20 Need 2 units to count to 127. Counter is re-loaded with 0s when count reaches 128. An alternative version would AND output bits 0 through 6 and assert Load while the count is 127. A_count[0] A_count[1] A_count[2] A_count[3] A_count[4] A_count[5] A_count[6] A_count[7] 27 = 128 Count Fig. 6.14 C_out Count = 1 Fig. 6.14 C_out 0 Load Load Data_in[0] Data_in[1] Data_in[2] CLK Clear Data_in[3] Data_in[4] Data_in[5] Data_in[6] Data_in[7] CLK Clear Load Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 6.21 177 (a) JA0 = LI0 + L'C KA0 = LI'0 + L'C (b) J = [L(LI)']'(L + C) = (L' + LI)(L + C) LI + L'C + LIC = LI + L'C (use a map) K = (LI)' (L + C) = (L' + I')(L + C) = LI' + L'C 6.22 C_out Fig. 6.14 Count = 1 C_out Load CLK Clear = 1 Fig. 6.14 0 0 Count sequence: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 Count sequence: 6, 7, 8, 9, 10, 11, 12 13, 14, 15 Count = 1 Load CLK Clear = 1 1 C_out Fig. 6.14 Count = 1 Load = 0 CLK Clear 0 Count sequence: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 6.23 Use a 4-bit counter and a flip-flop (initially at 0). A start signal sets the flip-flop, which in turn enables the counter. On the count of 11 (binary 1011) reset the flip-flop to 0 to disable the count (with the value of 0000 ). Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 178 6.24 Present Next state state Flip-flop inputs ABC ABC TA TB TC 0 1 000 001 0 1 0 001 011 0 x x 010 xxx x 1 0 011 111 1 1 0 100 000 1 x x 101 xxx x 1 0 110 100 0 0 1 111 110 0 A 00 0 A B BC 1 01 11 m0 m1 m3 m4 m5 m7 1 x A 10 m2 1 00 x 0 m6 B BC A 1 01 m0 m1 m4 m5 1 x C 0 A B 1 m0 01 1 m4 11 m3 m2 m5 m7 m6 1 A 10 m1 x x m6 x 1 B 00 0 A 1 m0 1 m4 01 11 10 m1 m3 m2 m5 m7 m6 x 1 x C TC = AC + A'B'C' 101 101 No self-correcting 6.25 m7 BC C TC = A C 010 m2 TB = B C BC 00 10 m3 C TA = A B A 11 010 100 Self-correcting (a) Use a 6-bit ring counter. (b) Counter of Fig. 6.16 6.26 C B A 20 21 22 3x8 Decoder 0 1 2 4 5 6 T0 T1 T2 T4 T5 T6 The clock generator has a period of 12.5 ns. Use a 2-bit counter to count four pulses. 80/4 = 20 MHz; cycle time = 1000 x 10-9 /20 = 50 ns. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 179 6.27 Present Next state state Flip-flop inputs ABC ABC JA KA JB KB JC KC 000 001 010 011 100 101 110 111 001 010 011 100 100 110 000 xxx 0 0 0 1 x x x x x x x x x x x x 0 1 x x 0 1 x x x x 0 1 0 x 1 x 1 x 1 x 1 x 0 x A 00 0 A B BC 1 01 11 m0 m1 m3 m4 m5 m7 x x A 10 m2 1 m6 x A B BC 00 0 x x 1 x 1 x 1 x x 1 m0 x m4 01 m1 x m5 0 A 1 01 m1 m4 m5 1 1 11 m3 m7 A 10 m2 x m6 x x 00 0 x A 1 0 A 1 m4 1 1 01 m5 x x m0 m4 x x 01 m1 m5 x x 11 m3 m7 10 m2 1 m6 x 1 C B m1 1 KB = A + C BC 00 x B C m0 m6 x BC JB = C A x C B 00 10 m2 KA = B BC m0 m3 m7 C JA = BC A 11 11 m3 m7 x x A 10 m2 1 m6 A C 1 m0 m4 x x 01 m1 m5 1 1 11 m3 m7 1 x 10 m2 m6 x x C JC = A' + B' 111 00 0 B BC KC = 1 001 Self-correcting Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 180 6.28 Present Next state state ABC ABC 000 001 010 011 100 101 110 111 A 001 010 100 xxx 110 xxx 000 xxx A 00 1 m0 m4 1 1 01 m1 m5 11 m3 x m7 x x m3 m4 m5 m7 1 x A 1 A x 10 m2 x 1 m6 x C DA = A B BC B 00 0 m6 11 m1 10 m2 01 m0 B 00 1 B BC 0 BC 0 A A 1 m0 m4 1 01 11 m1 m3 m5 m7 C x 10 m2 x m6 x C DB = AB' + C DC = A'B'C' Self-correcting 111 001 110 111 010 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 6.29 181 (a) The 8 valid states are listed in Fig. 8.18(b), with the sequence: 0, 8, 12, 14, 15, 7, 3, 1, 0, .... The 8 unused states and their next states are shown below: Next state State All invalid states ABCE ABCE 0000 0100 0101 0110 1001 1010 1011 1101 1001 1010 0010 1011 0100 1101 0101 0110 9 10 2 11 4 13 5 6 (b) Modification: DC = (A + C)B. D Q A D Q B D Q C D Q Q' E E' clk The valid states are the same as in (a). The unused states have the following sequences: 10→ 13→ 6→11→ 5→ 0. The final states, 0 and 8, are valid. 2→ 9→ 4→ 8 and Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 182 6.30 D Q A D Q B D C Q D Q D D Q Q' clk E E' The 5-bit Johnson counter has the following state sequence: ABCDE decoded output: 00000 A'E' 10000 AB' 11000 BC' 11100 CD' 11110 DE' 11111 A'E' 01111 AB' 00111 BC' 00011 CD' 00001 DE' 6.31 module Reg_4_bit_beh (output reg A3, A2, A1, A0, input I3, I2, I1, I0, Clock, Clear); always @ (posedge Clock, negedge Clear) if (Clear == 0) {A3, A2, A1, A0} <= 4'b0; else {A3, A2, A1, A0} <= {I3, I2, I1, I0}; endmodule module Reg_4_bit_Str (output A3, A2, A1, A0, input I3, I2, I1, I0, Clock, Clear); DFF M3DFF (A3, I3, Clock, Clear); DFF M2DFF (A2, I2, Clock, Clear); DFF M1DFF (A1, I1, Clock, Clear); DFF M0DFF (A0, I0, Clock, Clear); endmodule module DFF(output reg Q, input D, clk, clear); always @ (posedge clk, posedge clear) if (clear == 0) Q <= 0; else Q <= D; endmodule module t_Reg_4_bit (); wire A3_beh, A2_beh, A1_beh, A0_beh; wire A3_str, A2_str, A1_str, A0_str; reg I3, I2, I1, I0, Clock, Clear; wire [3: 0] I_data = {I3, I2, I1, I0}; wire [3: 0] A_beh = {A3_beh, A2_beh, A1_beh, A0_beh}; wire [3: 0] A_str = {A3_str, A2_str, A1_str, A0_str}; Reg_4_bit_beh M_beh (A3_beh, A2_beh, A1_beh, A0_beh, I3, I2, I1, I0, Clock, Clear); Reg_4_bit_Str M_str (A3_str, A2_str, A1_str, A0_str, I3, I2, I1, I0, Clock, Clear); initial #100 $finish; initial begin Clock = 0; forever #5 Clock = ~Clock; end initial begin Clear = 0; #2 Clear = 1; end integer K; initial begin for (K = 0; K < 16; K = K + 1) begin {I3, I2, I1, I0} = K; #10 ; end end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 183 Name 0 50 100 Clock Clear I_data[3:0] 0 1 2 3 4 5 6 7 8 9 I3 I2 I1 I0 A_beh[3:0] 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 A3_beh A2_beh A1_beh A0_beh A_str[3:0] A3_str A2_str A1_str A0_str 6.32 (a) module Reg_4_bit_Load (output reg A3, A2, A1, A0, input I3, I2, I1, I0, Load, Clock, Clear); always @ (posedge Clock, negedge Clear) if (Clear == 0) {A3, A2, A1, A0} <= 4'b0; else if (Load) {A3, A2, A1, A0} <= {I3, I2, I1, I0}; endmodule module t_Reg_4_Load (); wire A3_beh, A2_beh, A1_beh, A0_beh; reg I3, I2, I1, I0, Load, Clock, Clear; wire [3: 0] I_data = {I3, I2, I1, I0}; wire [3: 0] A_beh = {A3_beh, A2_beh, A1_beh, A0_beh}; Reg_4_bit_Load M0 (A3_beh, A2_beh, A1_beh, A0_beh, I3, I2, I1, I0, Load, Clock, Clear); initial #100 $finish; initial begin Clock = 0; forever #5 Clock = ~Clock; end initial begin Clear = 0; #2 Clear = 1; end integer K; initial fork #20 Load = 1; #30 Load = 0; #50 Load = 1; join initial begin for (K = 0; K < 16; K = K + 1) begin {I3, I2, I1, I0} = K; #10 ; end end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 184 Name 0 50 100 Clock Clear Load I_data[3:0] 0 1 2 3 4 5 6 7 8 9 I_data[3] I_data[2] I_data[1] I_data[0] A_beh[3:0] 0 2 5 6 7 8 9 A_beh[3] A_beh[2] A_beh[1] A_beh[0] (b) module Reg_4_bit_Load_str (output A3, A2, A1, A0, input I3, I2, I1, I0, Load, Clock, Clear); wire y3, y2, y1, y0; mux_2 M3 (y3, A3, I3, Load); mux_2 M2 (y2, A2, I2, Load); mux_2 M1 (y1, A1, I1, Load); mux_2 M0 (y0, A0, I0, Load); DFF M3DFF (A3, y3, Clock, Clear); DFF M2DFF (A2, y2, Clock, Clear); DFF M1DFF (A1, y1, Clock, Clear); DFF M0DFF (A0, y0, Clock, Clear); endmodule module DFF(output reg Q, input D, clk, clear); always @ (posedge clk, posedge clear) if (clear == 0) Q <= 0; else Q <= D; endmodule module mux_2 (output y, input a, b, sel); assign y = sel ? a: b; endmodule module t_Reg_4_Load_str (); wire A3, A2, A1, A0; reg I3, I2, I1, I0, Load, Clock, Clear; wire [3: 0] I_data = {I3, I2, I1, I0}; wire [3: 0] A = {A3, A2, A1, A0}; Reg_4_bit_Load_str M0 (A3, A2, A1, A0, I3, I2, I1, I0, Load, Clock, Clear); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 185 initial #100 $finish; initial begin Clock = 0; forever #5 Clock = ~Clock; end initial begin Clear = 0; #2 Clear = 1; end integer K; initial fork #20 Load = 1; #30 Load = 0; #50 Load = 1; #80 Load = 0; join initial begin for (K = 0; K < 16; K = K + 1) begin {I3, I2, I1, I0} = K; #10 ; end end endmodule Name 0 60 Clock Clear Load I_data[3:0] A[3:0] 0 1 2 x 3 4 3 5 6 4 7 8 9 8 (c) module Reg_4_bit_Load_beh (output reg A3, A2, A1, A0, input I3, I2, I1, I0, Load, Clock, Clear); always @ (posedge Clock, negedge Clear) if (Clear == 0) {A3, A2, A1, A0} <= 4'b0; else if (Load) {A3, A2, A1, A0} <= {I3, I2, I1, I0}; endmodule module Reg_4_bit_Load_str (output A3, A2, A1, A0, input I3, I2, I1, I0, Load, Clock, Clear); wire y3, y2, y1, y0; mux_2 M3 (y3, A3, I3, Load); mux_2 M2 (y2, A2, I2, Load); mux_2 M1 (y1, A1, I1, Load); mux_2 M0 (y0, A0, I0, Load); DFF M3DFF (A3, y3, Clock, Clear); DFF M2DFF (A2, y2, Clock, Clear); DFF M1DFF (A1, y1, Clock, Clear); DFF M0DFF (A0, y0, Clock, Clear); endmodule module DFF(output reg Q, input D, clk, clear); always @ (posedge clk, posedge clear) if (clear == 0) Q <= 0; else Q <= D; endmodule module mux_2 (output y, input a, b, sel); assign y = sel ? a: b; endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 186 module t_Reg_4_Load_str (); wire A3_beh, A2_beh, A1_beh, A0_beh; wire A3_str, A2_str, A1_str, A0_str; reg I3, I2, I1, I0, Load, Clock, Clear; wire [3: 0] I_data, A_beh, A_str; assign I_data = {I3, I2, I1, I0}; assign A_beh = {A3_beh, A2_beh, A1_beh, A0_beh}; assign A_str = {A3_str, A2_str, A1_str, A0_str}; Reg_4_bit_Load_str M0 (A3_beh, A2_beh, A1_beh, A0_beh, I3, I2, I1, I0, Load, Clock, Clear); Reg_4_bit_Load_str M1 (A3_str, A2_str, A1_str, A0_str, I3, I2, I1, I0, Load, Clock, Clear); initial #100 $finish; initial begin Clock = 0; forever #5 Clock = ~Clock; end initial begin Clear = 0; #2 Clear = 1; end integer K; initial fork #20 Load = 1; #30 Load = 0; #50 Load = 1; #80 Load = 0; join initial begin for (K = 0; K < 16; K = K + 1) begin {I3, I2, I1, I0} = K; #10 ; end end endmodule Name 0 60 Clock Clear Load I_data[3:0] 0 1 2 3 4 5 6 7 8 9 A_beh[3:0] x 3 4 8 A_str[3:0] x 3 4 8 6.33 // Stimulus for testing the binary counter of Example 6-3 module testcounter; reg Count, Load, CLK, Clr; reg [3: 0] IN; wire C0; wire [3: 0] A; Binary_Counter_4_Par_Load M0 ( A, // Data output C0, // Output carry IN, // Data input Count, // Active high to count Load, // Active high to load CLK, // Positive edge sensitive Clr // Active low ); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 187 always #5 CLK = ~CLK; initial begin Clr = 0; // Clear de-asserted CLK = 1; // Clock initialized high Load = 0; Count = 1; // Enable count #5 Clr = 1; // Clears count, then counts for five cycles #50 Load = 1; IN = 4'b1100; // Count is set to 4'b1100 (12`0) #10 Load = 0; #70 Count = 0; // Count is deasserted at t = 135 #20 $finish; // Terminate simulation end endmodule // Four-bit binary counter with parallel load // See Figure 6-14 and Table 6-6 module Binary_Counter_4_Par_Load ( output reg [3:0] A_count, // Data output output C_out, // Output carry input [3:0] Data_in, // Data input input Count, // Active high to count Load, // Active high to load CLK, // Positive edge sensitive Clear // Active low ); assign C_out = Count & (~Load) & (A_count == 4'b1111); always @ (posedge CLK, negedge Clear) if (~Clear) A_count <= 4'b0000; else if (Load) A_count <= Data_in; else if (Count) A_count <= A_count + 1'b1; else A_count <= A_count; // redundant statement endmodule // Note: a preferred description if the clock is given by: // initial begin CLK = 0; forever #5 CLK = ~CLK; end Name 0 60 120 CLK Clr Load x IN[3:0] c Count A[3:0] 0 1 2 3 4 5 c d e f 0 1 2 3 C0 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 188 6.34 module Shiftreg (SI, SO, CLK); input SI, CLK; output SO; reg [3: 0] Q; assign SO = Q[0]; always @ (posedge CLK) Q = {SI, Q[3: 1]}; endmodule // Test plan // // Verify that data shift through the register // Set SI =1 for 4 clock cycles // Hold SI =1 for 4 clock cycles // Set SI = 0 for 4 clock cycles // Verify that data shifts out of the register correctly module t_Shiftreg; reg SI, CLK; wire SO; Shiftreg M0 (SI, SO, CLK); initial #130 $finish; initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork SI = 1'b1; #80 SI = 0; join endmodule Name 0 60 120 CLK SI SO Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 6.35 189 (a) Note that Load has priority over Clear. module Prob_6_35a (output [3: 0] A, input [3:0] I, input Load, Clock, Clear); Register_Cell R0 (A[0], I[0], Load, Clock, Clear); Register_Cell R1 (A[1], I[1], Load, Clock, Clear); Register_Cell R2 (A[2], I[2], Load, Clock, Clear); Register_Cell R3 (A[3], I[3], Load, Clock, Clear); endmodule module Register_Cell (output A, input I, Load, Clock, Clear); DFF M0 (A, D, Clock); not (Load_b, Load); not (w1, Load_b); not (Clear_b, Clear); and (w2, I, w1); and (w3, A, Load_b, Clear_b); or (D, w2, w3); endmodule module DFF (output reg Q, input D, clk); always @ (posedge clk) Q <= D; endmodule module t_Prob_6_35a ( ); wire [3: 0] A; reg [3: 0] I; reg Clock, Clear, Load; Prob_6_35a M0 ( A, I, Load, Clock, Clear); initial #150 $finish; initial begin Clock = 0; forever #5 Clock = ~Clock; end initial fork I = 4'b1010;Clear = 1; #40 Clear = 0; Load = 0; #20 Load = 1; #40 Load = 0; join endmodule Name 0 60 120 Clock Clear Load a I[3:0] A[3:0] 0 a 0 (b) Note: The solution below replaces the solution given on the preliminary CD. module Prob_6_35b (output reg [3: 0] A, input [3:0] I, input Load, Clock, Clear); always @ (posedge Clock) if (Load) A <= I; else if (Clear) A <= 4'b0; //else A <= A; // redundant statement Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 190 endmodule module t_Prob_6_35b ( ); wire [3: 0] A; reg [3: 0] I; reg Clock, Clear, Load; Prob_6_35b M0 ( A, I, Load, Clock, Clear); initial #150 $finish; initial begin Clock = 0; forever #5 Clock = ~Clock; end initial fork I = 4'b1010; Clear = 1; #60 Clear = 0; Load = 0; #20 Load = 1; #40 Load = 0; join endmodule Name 0 60 120 Clock Clear Load a I[3:0] A[3:0] 0 a 0 (c) module Prob_6_35c (output [3: 0] A, input [3:0] I, input Shift, Load, Clock); Register_Cell R0 (A[0], I[0], A[1], Shift, Load, Clock); Register_Cell R1 (A[1], I[1], A[2], Shift, Load, Clock); Register_Cell R2 (A[2], I[2], A[3], Shift, Load, Clock); Register_Cell R3 (A[3], I[3], A[0], Shift, Load, Clock); endmodule module Register_Cell (output A, input I, Serial_in, Shift, Load, Clock); DFF M0 (A, D, Clock); not (Shift_b, Shift); not (Load_b, Load); and (w1, Shift, Serial_in); and (w2, Shift_b, Load, I); and (w3, A, Shift_b, Load_b); or (D, w1, w2, w3); endmodule module DFF (output reg Q, input D, clk); always @ (posedge clk) Q <= D; endmodule module t_Prob_6_35c ( ); wire [3: 0] A; reg [3: 0] I; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 191 reg Clock, Shift, Load; Prob_6_35c M0 (A, I, Shift, Load, Clock); initial #150 $finish; initial begin Clock = 0; forever #5 Clock = ~Clock; end initial fork I = 4'b1010; Load = 0; Shift = 0; #20 Load = 1; #40 Load = 0; #50 Shift = 1; join endmodule Name 0 60 120 Clock Shift Load a I[3:0] A[3:0] x a 5 a 5 a 5 a 5 a 5 (d) module Prob_6_35d (output reg [3: 0] A, input [3:0] I, input Shift, Load, Clock, Clear); always @ (posedge Clock) if (Shift) A <= {A[0], A[3:1]}; else if (Load) A <= I; else if (Clear) A <= 4'b0; //else A <= A; // redundant statement endmodule module t_Prob_6_35d ( ); wire [3: 0] A; reg [3: 0] I; reg Clock, Clear, Shift, Load; Prob_6_35d M0 ( A, I, Shift, Load, Clock, Clear); initial #150 $finish; initial begin Clock = 0; forever #5 Clock = ~Clock; end initial fork I = 4'b1010; Clear = 1; #100 Clear = 0; Load = 0; #20 Load = 1; #40 Load = 0; #30 Shift = 1; #90 Shift = 0; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 192 Name 0 60 120 Clock Clear Shift Load a I[3:0] A[3:0] 0 a 5 a 5 a 5 a 0 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 193 (e) module Shift_Register (output [3: 0] A_par, input [3: 0] I_par, input MSB_in, LSB_in, s1, s0, CLK, Clear); wire y3, y2, y1, y0; DFF D3 (A_par[3], y3, CLK, Clear); DFF D2 (A_par[2], y2, CLK, Clear); DFF D1 (A_par[1], y1, CLK, Clear); DFF D0 (A_par[0], y0, CLK, Clear); MUX_4x1 M3 (y3, I_par[3], A_par[2], MSB_in, A_par[3], s1, s0); MUX_4x1 M2 (y2, I_par[2], A_par[1], A_par[3], A_par[2], s1, s0); MUX_4x1 M1 (y1, I_par[1], A_par[0], A_par[2], A_par[1], s1, s0); MUX_4x1 M0 (y0, I_par[0], LSB_in, A_par[1], A_par[0], s1, s0); endmodule module MUX_4x1 (output reg y, input I3, I2, I1, I0, s1, s0); always @ (I3, I2, I1, I0, s1, s0) case ({s1, s0}) 2'b11: y = I3; 2'b10: y = I2; 2'b01: y = I1; 2'b00: y = I0; endcase endmodule module DFF (output reg Q, input D, clk, reset_b); always @ (posedge clk, negedge reset_b) if (reset_b == 0) Q <= 0; else Q <= D; endmodule module t_Shift_Register ( ); wire [3: 0] A_par; reg [3: 0] I_par; reg MSB_in, LSB_in, s1, s0, CLK, Clear; Shift_Register M_SR( A_par, I_par, MSB_in, LSB_in, s1, s0, CLK, Clear); initial #300 $finish; initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork MSB_in = 0; LSB_in = 0; Clear = 0; // Active-low reset s1 = 0; s0 = 0; // No change #10 Clear = 1; #10 I_par = 4'hA; #30 begin s1 = 1; s0 = 1; end // 00: load I_par into A_par #50 s1 = 0; // 01: shift right (1010 to 0101 to 0010 to 0001 to 0000) #90 begin s1 = 1; s0 = 1; end // 11: reload A with 1010 #100 s0 = 0; // 10: shift left (1010 to 0100 to 1000 to 000) #140 begin s1 = 1; s0 = 1; MSB_in = 1; LSB_in = 1; end // Repeat with MSB and LSB #150 s1 = 0; #190 begin s1 = 1; s0 = 1; end // reload with A = 1010 #200 s0 = 0; // Shift left #220 s1 = 0; // Pause #240 s1 = 1; // Shift left join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 194 No change Name Shift right Load Load 0 Shift left 90 180 270 CLK Clear s1 s0 I_par[3:0] x a MSB_in LSB_in A_par[3:0] 0 a 5 2 1 0 a 4 8 0 a d e f a 5 b 7 (f) module Shift_Register_BEH (output [3: 0] A_par, input [3: 0] I_par, input MSB_in, LSB_in, s1, s0, CLK, Clear); always @ (posedge CLK, negedge Clear) if (Clear == 0) A_par <= 4'b0; else case ({s1, s0}) 2'b11: A_par <= I_par; 2'b01: A_par <= {MSB_in, A_par[3: 1]}; 2'b10: A_par <= {A_par[2: 0], LSB_in}; 2'b00: A_par <=A_par; endcase endmodule module t_Shift_Register ( ); wire [3: 0] A_par; reg [3: 0] I_par; reg MSB_in, LSB_in, s1, s0, CLK, Clear; Shift_Register_BEH M_SR( A_par, I_par, MSB_in, LSB_in, s1, s0, CLK, Clear); initial #300 $finish; initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork MSB_in = 0; LSB_in = 0; Clear = 0; // Active-low reset s1 = 0; s0 = 0; // No change #10 Clear = 1; #10 I_par = 4'hA; #30 begin s1 = 1; s0 = 1; end // 00: load I_par into A_par #50 s1 = 0; // 01: shift right (1010 to 0101 to 0010 to 0001 to 0000) #90 begin s1 = 1; s0 = 1; end // 11: reload A with 1010 #100 s0 = 0; // 10: shift left (1010 to 0100 to 1000 to 000) #140 begin s1 = 1; s0 = 1; MSB_in = 1; LSB_in = 1; end // Repeat with MSB and LSB #150 s1 = 0; #190 begin s1 = 1; s0 = 1; end // reload with A = 1010 #200 s0 = 0; // Shift left #220 s1 = 0; // Pause #240 s1 = 1; // Shift left join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. f 195 Name 0 90 180 270 CLK Clear s1 s0 I_par[3:0] x a MSB_in LSB_in A_par[3:0] 0 a 5 2 1 0 a 4 8 0 a d e f a 5 b 7 (g) module Ripple_Counter_4bit_a (output [3: 0] A, input Count, reset_b); reg A0, A1, A2, A3; assign A = {A3, A2, A1, A0}; always @ (negedge Count, negedge reset_b) if (reset_b == 0) A0 <= 0; else if (T) A0 <= ~A0; always @ (negedge A0, negedge reset_b) if (reset_b == 0) A1 <= 0; else if (T) A1 <= ~A1; always @ (negedge A1, negedge reset_b) if (reset_b == 0) A2 <= 0; else if (T) A2 <= ~A2; always @ (negedge A2, negedge reset_b) if (reset_b == 0) A3 <= 0; else if (T) A3 <= ~A3; endmodule module t_Ripple_Counter_4bit (); wire [3: 0] A; reg Count, reset_b; Ripple_Counter_4bit_a M0 (A, Count, reset_b); initial #300 $finish; initial fork reset_b = 0; #60 reset_b = 1; // Active-low reset Count = 1; #15 Count = 0; #30 Count = 1; #85 begin Count = 0; forever #10 Count = ~Count; end join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. f 196 module Ripple_Counter_4bit_b (output [3: 0] A, input Count, reset_b); reg A0, A1, A2, A3; assign A = {A3, A2, A1, A0}; always @ (negedge Count, negedge reset_b) if (reset_b == 0) A0 <= 0; else A0 <= ~A0; always @ (negedge A0, negedge reset_b) if (reset_b == 0) A1 <= 0; else A1 <= ~A1; always @ (negedge A1, negedge reset_b) if (reset_b == 0) A2 <= 0; else A2 <= ~A2; always @ (negedge A2, negedge reset_b) if (reset_b == 0) A3 <= 0; else A3 <= ~A3; endmodule module t_Ripple_Counter_4bit (); wire [3: 0] A; reg Count, reset_b; Ripple_Counter_4bit_b M0 (A, Count, reset_b); initial #300 $finish; initial fork reset_b = 0; #60 reset_b = 1; // Active-low reset Count = 1; #15 Count = 0; #30 Count = 1; #85 begin Count = 0; forever #10 Count = ~Count; end join endmodule Name 0 90 180 270 Count reset_b A[3:0] (h) 0 1 2 3 4 5 6 7 8 9 Note: This version of the solution situates the data shift registers in the test bench. module Serial_Subtractor (output SO, input SI_A, SI_B, shift_control, clock, reset_b); // See Fig. 6.5 and Problem 6.9a (2s complement serial subtractor) reg [1: 0] sum; wire mem = sum[1]; assign SO = sum[0]; always @ (posedge clock, negedge reset_b) if (reset_b == 0) begin sum <= 2'b10; end else if (shift_control) begin sum <= SI_A + (!SI_B) + sum[1]; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. a b 197 end endmodule module t_Serial_Subtractor (); wire SI_A, SI_B; reg shift_control, clock, reset_b; Serial_Subtractor M0 (SO, SI_A, SI_B, shift_control, clock, reset_b); initial #250 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork shift_control = 0; #10 reset_b = 0; #20 reset_b = 1; #22 shift_control = 1; #105 shift_control = 0; #112 reset_b = 0; #114 reset_b = 1; #122 shift_control = 1; #205 shift_control = 0; join reg [7: 0] A, B, SO_reg; wire s7; assign s7 = SO_reg[7]; assign SI_A = A[0]; assign SI_B = B[0]; wire SI_B_bar = ~SI_B; initial fork A = 8'h5A; B = 8'h0A; #122 A = 8'h0A; #122 B = 8'h5A; join always @ (negedge clock, negedge reset_b) if (reset_b == 0) SO_reg <= 0; else if (shift_control == 1) begin SO_reg <= {SO, SO_reg[7: 1]}; A <= A >> 1; B <= B >> 1; end wire negative = !M0.sum[1]; wire [7: 0] magnitude = (!negative)? SO_reg: 1'b1 + ~SO_reg; endmodule Simulation results are shown for 5Ah – 0Ah = 50h = 80 d and 0Ah – 5Ah = -80. The magnitude of the result is also shown. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 05 5 0a 10 B[7:0] B[7:0] magnitude[7:0] 0 x SO_reg[7:0] x 0 xx SO_reg[7:0] negative 00 x 2 02 22 16 40 sum[1:0] mem SO SI_B_bar SI_A 2 45 90 SI_B 2d 5a A[7:0] 0 A[7:0] shift_control reset_b clock Default Name 1 01 11 0b 5 05 3 128 128 80 2 02 2 64 64 40 1 01 80 3 a0 160 160 0 00 80 80 50 0 00 90 5a 10 0a 120 2 45 2d 5 05 0 0 00 22 16 2 02 11 0b 1 01 5 05 160 128 128 80 1 2 02 64 192 c0 1 01 0 00 0 160 96 60 0 00 b0 80 176 1 200 198 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 199 (i) See Prob. 6.35h. (j) module Serial_Twos_Comp (output y, input [7: 0] data, input load, shift_control, Clock, reset_b); reg [7: 0] SReg; reg Q; wire SO = SReg [0]; assign y = SO ^ Q; always @ (posedge Clock, negedge reset_b) if (reset_b == 0) begin SReg <= 0; Q <= 0; end else begin if (load) SReg = data; else if (shift_control) begin Q <= Q | SO; SReg <= {y, SReg[7: 1]}; end end endmodule module t_Serial_Twos_Comp (); wire y; reg [7: 0] data; reg load, shift_control, Clock, reset_b; Serial_Twos_Comp M0 (y, data, load, shift_control, Clock, reset_b); reg [7: 0] twos_comp; always @ (posedge Clock, negedge reset_b) if (reset_b == 0) twos_comp <= 0; else if (shift_control && !load) twos_comp <= {y, twos_comp[7: 1]}; initial #200 $finish; initial begin Clock = 0; forever #5 Clock = ~Clock; end initial begin #2 reset_b = 0; #4 reset_b = 1; end initial fork data = 8'h5A; #20 load = 1; #30 load = 0; #50 shift_control = 1; #50 begin repeat (9) @ (posedge Clock) ; shift_control = 0; end join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 200 Name 0 50 100 Clock reset_b 5a data[7:0] load shift_control SReg[7:0] 00 5a 2d 96 cb 65 32 99 4c 80 c0 60 30 98 4c a6 y twos_comp[7:0] (k) 00 From the solution to Problem 6.13: A1 4-Bit Ripple Counter Clear Asynchronous, active-low) A2 0 1 0 A3 1 A4 module Prob_6_35k_BCD_Counter (output A1, A2, A3, A4, input clk, reset_b); wire {A1, A2, A3, A4} = A; nand (Clear, A2, A4); Ripple_Counter_4bit M0 (A, Clear, reset_b); endmodule module Ripple_Counter_4bit (output [3: 0] A, input Count, reset_b); reg A0, A1, A2, A3; assign A = {A3, A2, A1, A0}; always @ (negedge Count, negedge reset_b) if (reset_b == 0) A0 <= 0; else A0 <= ~A0; always @ (negedge A0, negedge reset_b) if (reset_b == 0) A1 <= 0; else A1 <= ~A1; always @ (negedge A1, negedge reset_b) if (reset_b == 0) A2 <= 0; else A2 <= ~A2; always @ (negedge A2, negedge reset_b) if (reset_b == 0) A3 <= 0; else A3 <= ~A3; endmodule module t_ Prob_6_35k_BCD_Counter (); wire [3: 0] A; reg Count, reset_b; Prob_6_35k_BCD_Counter M0 (A1, A2, A3, A4, reset_b); initial #300 $finish; initial fork reset_b = 0; #60 reset_b = 1; // Active-low reset /* Count = 1; #15 Count = 0; #30 Count = 1; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. a6 201 #85 begin Count = 0; forever #10 Count = ~Count; end*/ join endmodule (l) module Prob_6_35l_Up_Dwn_Beh (output reg [3: 0] A, input CLK, Up, Down, reset_b); always @ (posedge CLK, negedge reset_b) if (reset_b ==0) A <= 4'b0000; else case ({Up, Down}) 2'b10: A <= A + 4'b0001; // Up 2'b01: A <= A - 4'b0001; // Down default: A <= A; // Suspend (Redundant statement) endcase endmodule module t_Prob_6_35l_Up_Dwn_Beh (); wire [3: 0] A; reg CLK, Up, Down, reset_b; Prob_6_35l_Up_Dwn_Beh M0 (A, CLK, Up, Down, reset_b); initial #300 $finish; initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork Down = 0; Up= 0; #10 reset_b = 0; #20 reset_b = 1; #40 Up = 1; #150 Down = 1; #220 Up = 0; #280 Down = 0; join endmodule Name 0 90 180 270 CLK reset_b Up Down A[3:0] 6.36 x 0 1 2 3 4 5 6 7 8 9 a b a 9 8 7 6 (a) // See Fig. 6.13., 4-bit Up-Down Binary Counter module Prob_6_36_Up_Dwn_Beh (output reg [3: 0] A, input CLK, Up, Down, reset_b); always @ (posedge CLK, negedge reset_b) if (reset_b ==0) A <= 4'b0000; else if (Up) A <= A + 4'b0001; else if (Down) A <= A - 4'b0001; endmodule module t_Prob_6_36_Up_Dwn_Beh (); wire [3: 0] A; reg CLK, Up, Down, reset_b; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 5 202 Prob_6_36_Up_Dwn_Beh M0 (A, CLK, Up, Down, reset_b); initial #300 $finish; initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork Down = 0; Up= 0; #10 reset_b = 0; #20 reset_b = 1; #40 Up = 1; #150 Down = 1; #220 Up = 0; #280 Down = 0; join endmodule Name 0 80 160 240 CLK reset_b Up Down A[3:0] x 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 1 0 f e d c (b) module Prob_6_36_Up_Dwn_Str (output [3: 0] A, input CLK, Up, Down, reset_b); wire Down_3, Up_3, Down_2, Up_2, Down_1, Up_1; wire A_0b, A_1b, A_2b, A_3b; stage_register SR3 (A[3], A_3b, Down_3, Up_3, Down_2, Up_2, A[2], A_2b, CLK, reset_b); stage_register SR2 (A[2], A_2b, Down_2, Up_2, Down_1, Up_1, A[1], A_1b, CLK, reset_b); stage_register SR1 (A[1], A_1b, Down_1, Up_1, Down_not_Up, Up, A[0], A_0b, CLK, reset_b); not (Up_b, Up); and (Down_not_Up, Down, Up_b); or (T, Up, Down_not_Up); Toggle_flop TF0 (A[0], A_0b, T, CLK, reset_b); endmodule module stage_register (output A, A_b, Down_not_Up_out, Up_out, input Down_not_Up, Up, A_in, A_in_b, CLK, reset_b); Toggle_flop T0 (A, A_b, T, CLK, reset_b); or (T, Down_not_Up_out, Up_out); and (Down_not_Up_out, Down_not_Up, A_in_b); and (Up_out, Up, A_in); endmodule module Toggle_flop (output reg Q, output Q_b, input T, CLK, reset_b); always @ (posedge CLK, negedge reset_b) if (reset_b == 0) Q <= 0; else Q <= Q ^ T; assign Q_b = ~Q; endmodule module t_Prob_6_36_Up_Dwn_Str (); wire [3: 0] A; reg CLK, Up, Down, reset_b; wire T3 = M0.SR3.T; wire T2 = M0.SR2.T; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 203 wire T1 = M0.SR1.T; wire T0 = M0.T; Prob_6_36_Up_Dwn_Str M0 (A, CLK, Up, Down, reset_b); initial #150 $finish; initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork Down = 0; Up= 0; #10 reset_b = 0; #20 reset_b = 1; #50 Up = 1; #140 Down = 1; #120 Up = 0; #140 Down = 0; join endmodule Name 0 70 140 210 280 CLK reset_b Up Down A[3:0] x 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 1 0 f e T0 T1 T2 T3 6.37 module Counter_if (output reg [3: 0] Count, input clock, reset); always @ (posedge clock , posedge reset) if (reset)Count <= 0; else if (Count == 0) Count <= 1; else if (Count == 1) Count <= 3; // Default interpretation is decimal else if (Count == 3) Count <= 7; else if (Count == 4) Count <= 0; else if (Count == 6) Count <= 4; else if (Count == 7) Count <= 6; else Count <= 0; endmodule module Counter_case (output reg [3: 0] Count, input clock, reset); always @ (posedge clock , posedge reset) if (reset)Count <= 0; else begin Count <= 0; case (Count) 0: Count <= 1; 1: Count <= 3; 3: Count <= 7; 4: Count <= 0; 6: Count <= 4; 7: Count <= 6; default: Count <= 0; endcase end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. d c 204 module Counter_FSM (output reg [3: 0] Count, input clock, reset); reg [2: 0] state, next_state; parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4, s5 = 5, s6 = 6, s7 = 7; always @ (posedge clock , posedge reset) if (reset) state <= s0; else state <= next_state; always @ (state) begin Count = 0; case (state) s0: begin next_state = s1; Count = 0; end s1: begin next_state = s2; Count = 1; end s2: begin next_state = s3; Count = 3; end s3: begin next_state = s4; Count = 7; end s4: begin next_state = s5; Count = 6; end s5: begin next_state = s6; Count = 4; end default: begin next_state = s0; Count = 0; end endcase end endmodule 6.38 (a) module Prob_6_38a_Updown (OUT, Up, Down, Load, IN, CLK); // Verilog 1995 output [3: 0] OUT; input [3: 0] IN; input Up, Down, Load, CLK; reg [3:0] OUT; always @ (posedge CLK) if (Load) OUT <= IN; else if (Up) OUT <= OUT + 4'b0001; else if (Down) OUT <= OUT - 4'b0001; else OUT <= OUT; endmodule module updown ( // Verilog 2001, 2005 output reg [3: 0] OUT, input [3: 0] IN, input Up, Down, Load, CLK ); Name 0 110 220 330 440 clock reset_b Load Down Up c data[3:0] count[3:0] 0 c d e f 0 1 3 4 5 7 8 9 b c c b a 8 7 6 4 3 1 0 f d c b 0 c (b) module Prob_6_38b_Updown (output reg [3: 0] OUT, input [3: 0] IN, input s1, s0, CLK); always @ (posedge CLK) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 205 case ({s1, s0}) 2'b00: OUT <= OUT + 4'b0001; 2'b01: OUT <= OUT - 4'b0001; 2'b10: OUT <= IN; 2'b11: OUT <= OUT; endcase endmodule module t_Prob_6_38b_Updown (); wire [3: 0] OUT; reg [3: 0] IN; reg s1, s0, CLK; Prob_6_38b_Updown M0 (OUT, IN, s1, s0, CLK); initial #150 $finish; initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork IN = 4'b1010; #10 begin s1 = 1; s0 = 0; end #20 begin s1 = 1; s0 = 1; end #40 begin s1 = 0; s0 = 0; end #80 begin s1 = 0; s0 = 1; end #120 begin s1 = 1; s0 = 1; end join endmodule Name // Load IN // no change // UP; // DOWN 0 60 120 CLK s1 s0 a IN[3:0] OUT[3:0] x a b c d e d c b a 6.39 module Prob_6_39_Counter_BEH (output reg [2: 0] Count, input Clock, reset_b); always @ (posedge Clock, negedge reset_b) if (reset_b == 0) Count <= 0; else case (Count) 0: Count <= 1; 1: Count <= 2; 2: Count <= 4; 4: Count <= 5; 5: Count <= 6; 6: Count <= 0; endcase endmodule module Prob_6_39_Counter_STR (output [2: 0] Count, input Clock, reset_b); supply1 PWR; wire Count_1_b = ~Count[1]; JK_FF M2 (Count[2], JK_FF M1 (Count[1], JK_FF M0 (Count[0], endmodule Count[1], Count[1], Clock, reset_b); Count[0], PWR, Clock, reset_b); Count_1_b, PWR, Clock, reset_b); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 206 module JK_FF (output reg Q, input J, K, clk, reset_b); always @ (posedge clk, negedge reset_b) if (reset_b == 0) Q <= 0; else case ({J,K}) 2'b00: Q <= Q; 2'b01: Q <= 0; 2'b10: Q <= 1; 2'b11: Q <= ~Q; endcase endmodule module t_Prob_6_39_Counter (); wire [2: 0] Count_BEH, Count_STR; reg Clock, reset_b; Prob_6_39_Counter_BEH M0_BEH (Count_STR, Clock, reset_b); Prob_6_39_Counter_STR M0_STR (Count_BEH, Clock, reset_b); initial #250 $finish; initial fork #1 reset_b = 0; #7 reset_b = 1; join initial begin Clock = 1; forever #5 Clock = ~Clock; end endmodule Name 0 60 120 Clock reset_b Count_BEH[2:0] 0 1 2 4 5 6 0 1 2 4 5 6 0 1 2 4 Count_STR[2:0] 0 1 2 4 5 6 0 1 2 4 5 6 0 1 2 4 6.40 module Prob_6_40 (output reg [0: 7] timer, input clk, reset_b); always @ (negedge clk, negedge reset_b) if (reset_b == 0) timer <= 8'b1000_0000; else case (timer) 8'b1000_0000: timer <= 8'b0100_0000; 8'b0100_0000: timer <= 8'b0010_0000; 8'b0010_0000: timer <= 8'b0001_0000; 8'b0001_0000: timer <= 8'b0000_1000; 8'b0000_1000: timer <= 8'b0000_0100; 8'b0000_0100: timer <= 8'b0000_0010; 8'b0000_0010: timer <= 8'b0000_0001; 8'b0000_0001: timer <= 8'b1000_0000; default: timer <= 8'b1000_0000; endcase endmodule module t_Prob_6_40 (); wire [0: 7] timer; reg clk, reset_b; Prob_6_40 M0 (timer, clk, reset_b); initial #250 $finish; initial fork #1 reset_b = 0; #7 reset_b = 1; join initial begin clk = 1; forever #5 clk = ~clk; end Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 207 endmodule Name 0 70 140 210 clk reset_b timer[0:7] 80 timer[0] timer[1] timer[2] timer[3] timer[4] timer[5] timer[6] timer[7] 6.41 module Prob_6_41_Switched_Tail_Johnson_Counter (output [0: 3] Count, input CLK, reset_b); wire Q_0b, Q_1b, Q_2b, Q_3b; DFF M3 (Count[3], Q_3b, Count[2], CLK, reset_b); DFF M2 (Count[2], Q_2b, Count[1], CLK, reset_b); DFF M1 (Count[1], Q_1b, Count[0], CLK, reset_b); DFF M0 (Count[0], Q_0b, Q_3b, CLK, reset_b); endmodule module DFF (output reg Q, output Q_b, input D, clk, reset_b); assign Q_b = ~Q; always @ (posedge clk, negedge reset_b) if (reset_b ==0) Q <= 0; else Q <= D; endmodule module t_Prob_6_41_Switched_Tail_Johnson_Counter (); wire [3: 0] Count; reg CLK, reset_b; wire s0 = ~ M0.Count[0] && ~M0.Count[3]; wire s1 = M0.Count[0] && ~M0.Count[1]; wire s2 = M0.Count[1] && ~M0.Count[2]; wire s3 = M0.Count[2] && ~M0.Count[3]; wire s4 = M0.Count[0] && M0.Count[3]; wire s5 = ~ M0.Count[0] && M0.Count[1]; wire s6 = ~ M0.Count[1] && M0.Count[2]; wire s7 = ~ M0.Count[2] && M0.Count[3]; Prob_6_41_Switched_Tail_Johnson_Counter M0 (Count, CLK, reset_b); initial #150 $finish; initial fork #1 reset_b = 0; #7 reset_b = 1; join initial begin CLK = 1; forever #5 CLK = ~CLK; end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 208 Name 0 60 120 CLK reset_b Count[3:0] 0 8 c e f 7 3 1 0 8 c e f 7 3 s0 s1 s2 s3 s4 s5 s6 s7 6.42 Because A is a register variable, it retains whatever value has been assigned to it until a new value is assigned. Therefore, the statement A <= A has the same effect as if the statement was omitted. 6.43 data D_in Shift_control load Clock Mux Mux D Q DFF [ module Prob_6_43_Str (output SO, input [7: 0] data, input load, Shift_control, Clock, reset_b); supply0 gnd; wire SO_A; Shift_with_Load M_A (SO_A, SO_A, data, load, Shift_control, Clock, reset_b); Shift_with_Load M_B (SO, SO_A, data, gnd, Shift_control, Clock, reset_b); endmodule module Shift_with_Load (output SO, input D_in, input [7: 0] data, input load, select, Clock, reset_b); wire [7: 0] Q; assign SO = Q[0]; SR_cell M7 (Q[7], D_in, data[7], load, select, Clock, reset_b); SR_cell M6 (Q[6], Q[7], data[6], load, select, Clock, reset_b); SR_cell M5 (Q[5], Q[6], data[5], load, select, Clock, reset_b); SR_cell M4 (Q[4], Q[5], data[4], load, select, Clock, reset_b); SR_cell M3 (Q[3], Q[4], data[3], load, select, Clock, reset_b); SR_cell M2 (Q[2], Q[3], data[2], load, select, Clock, reset_b); SR_cell M1 (Q[1], Q[2], data[1], load, select, Clock, reset_b); SR_cell M0 (Q[0], Q[1], data[0], load, select, Clock, reset_b); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 209 module SR_cell (output Q, input D, data, load, select, Clock, reset_b); wire y; DFF_with_load M0 (Q, y, data, load, Clock, reset_b); Mux_2 M1 (y, Q, D, select); endmodule module DFF_with_load (output reg Q, input D, data, load, Clock, reset_b); always @ (posedge Clock, negedge reset_b) if (reset_b == 0) Q <= 0; else if (load) Q <= data; else Q <= D; endmodule module Mux_2 (output reg y, input a, b, sel); always @ (a, b, sel) if (sel ==1) y = b; else y = a; endmodule module t_Fig_6_4_Str (); wire SO; reg load, Shift_control, Clock, reset_b; reg [7: 0] data, Serial_Data; Prob_6_43_Str M0 (SO, data, load, Shift_control, Clock, reset_b); always @ (posedge Clock, negedge reset_b) if (reset_b == 0) Serial_Data <= 0; else if (Shift_control ) Serial_Data <= {M0.SO_A, Serial_Data [7: 1]}; initial #200 $finish; initial begin Clock = 0; forever #5 Clock = ~Clock; end initial begin #2 reset_b = 0; #4 reset_b = 1; end initial fork data = 8'h5A; #20 load = 1; #30 load = 0; #50 Shift_control = 1; #50 begin repeat (9) @ (posedge Clock) ; Shift_control = 0; end join endmodule 0 Name 50 100 Clock reset_b load Shift_control 5a data[7:0] SO_A SO 96 4b a5 d2 69 b4 5a Q[7:0] 00 80 40 a0 d0 68 b4 5a Serial_Data[7:0] 00 80 40 a0 d0 68 b4 Q[7:0] 00 5a 2d 2d 2d 5a Alternative: a behavioral model for synthesis is given below. The behavioral description implies the need for a mux at the input to a D-type flip-flop. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 210 module Fig_6_4_Beh (output SO, input [7: 0] data, input load, Shift_control, Clock, reset_b); reg [7: 0] Shift_Reg_A, Shift_Reg_B; assign SO = Shift_Reg_B[0]; always @ (posedge Clock, negedge reset_b) if (reset_b == 0) begin Shift_Reg_A <= 0; Shift_Reg_B <= 0; end else if (load) Shift_Reg_A <= data; else if (Shift_control) begin Shift_Reg_A <= { Shift_Reg_A[0], Shift_Reg_A[7: 1]}; Shift_Reg_B <= {Shift_Reg_A[0], Shift_Reg_B[7: 1]}; end endmodule module t_Fig_6_4_Beh (); wire SO; reg load, Shift_control, Clock, reset_b; reg [7: 0] data, Serial_Data; Fig_6_4_Beh M0 (SO, data, load, Shift_control, Clock, reset_b); always @ (posedge Clock, negedge reset_b) if (reset_b == 0) Serial_Data <= 0; else if (Shift_control ) Serial_Data <= {M0.Shift_Reg_A[0], Serial_Data [7: 1]}; initial #200 $finish; initial begin Clock = 0; forever #5 Clock = ~Clock; end initial begin #2 reset_b = 0; #4 reset_b = 1; end initial fork data = 8'h5A; #20 load = 1; #30 load = 0; #50 Shift_control = 1; #50 begin repeat (9) @ (posedge Clock) ; Shift_control = 0; end join endmodule Name 0 50 100 150 Clock reset_b load Shift_control 5a data[7:0] Shift_Reg_A[7:0] Shift_Reg_B[7:0] 00 5a 2d 96 4b a5 d2 69 b4 5a 2d 00 80 40 a0 d0 68 b4 5a 2d 00 80 40 a0 d0 68 b4 SO Serial_Data[7:0] 5a 6.44 // See Figure 6.5 // Note: Sum is stored in shift register A; carry is stored in Q Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 211 // Note: Clear is active-low. module Prob_6_44_Str (output SO, input [7: 0] data_A, data_B, input S_in, load, Shift_control, CLK, Clear); supply0 gnd; wire sum, carry; assign SO = sum; wire SO_A, SO_B; Shift_Reg_gated_clock M_A (SO_A, sum, data_A, load, Shift_control, CLK, Clear); Shift_Reg_gated_clock M_B (SO_B, S_in, data_B, load, Shift_control, CLK, Clear); FA M_FA (carry, sum, SO_A, SO_B, Q); DFF_gated M_FF (Q, carry, Shift_control, CLK, Clear); endmodule module Shift_Reg_gated_clock (output SO, input S_in, input [7: 0] data, input load, Shift_control, Clock, reset_b); reg [7: 0] SReg; assign SO = SReg[0]; always @ (posedge Clock, negedge reset_b) if (reset_b == 0) SReg <= 0; else if (load) SReg <= data; else if (Shift_control) SReg <= {S_in, SReg[7: 1]}; endmodule module DFF_gated (output Q, input D, Shift_control, Clock, reset_b); DFF M_DFF (Q, D_internal, Clock, reset_b); Mux_2 M_Mux (D_internal, Q, D, Shift_control); endmodule module DFF (output reg Q, input D, Clock, reset_b); always @ (posedge Clock, negedge reset_b) if (reset_b == 0) Q <= 0; else Q <= D; endmodule module Mux_2 (output reg y, input a, b, sel); always @ (a, b, sel) if (sel ==1) y = b; else y = a; endmodule module FA (output reg carry, sum, input a, b, C_in); always @ (a, b, C_in) {carry, sum} = a + b + C_in; endmodule module t_Prob_6_44_Str (); wire SO; reg SI, load, Shift_control, Clock, Clear; reg [7: 0] data_A, data_B; Prob_6_44_Str M0 (SO, data_A, data_B, SI, load, Shift_control, Clock, Clear); initial #200 $finish; initial begin Clock = 0; forever #5 Clock = ~Clock; end initial begin #2 Clear = 0; #4 Clear = 1; end initial fork data_A = 8'hAA; data_B = 8'h55; SI = 0; #20 load = 1; #30 load = 0; //8'h ff; //8'h01; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 212 #50 Shift_control = 1; #50 begin repeat (8) @ (posedge Clock) ; #5 Shift_control = 0; end join endmodule Name 0 60 120 Clock Clear load Shift_control aah + 55h = {carry, sum} = {0, ffh} aa data_A[7:0] SReg[7:0] 00 aa d5 ea 00 55 2a 15 f5 fa fd fe ff 05 02 01 00 Q 55 data_B[7:0] SReg[7:0] 0a SO Name 0 60 120 Clock Clear load Shift_control ffh + 01h = {carry, sum} = {1, 00h} ff data_A[7:0] SReg[7:0] 00 ff 00 01 7f 3f 1f 0f 07 03 01 00 Q 01 data_B[7:0] SReg[7:0] 00 SO 6.45 module Prob_6_45 (output reg y_out, input start, clock, reset_bar); parameter s0 = 4'b0000, s1 = 4'b0001, s2 = 4'b0010, s3 = 4'b0011, s4 = 4'b0100, s5 = 4'b0101, s6 = 4'b0110, s7 = 4'b0111, s8 = 4'b1000; reg [3: 0] state, next_state; always @ (posedge clock, negedge reset_bar) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 213 if (!reset_bar) state <= s0; else state <= next_state; always @ (state, start) begin y_out = 1'b0; case (state) s0: if (start) next_state = s1; else next_state = s0; s1: begin next_state = s2; y_out = 1; end s2: begin next_state = s3; y_out = 1; end s3: begin next_state = s4; y_out = 1; end s4: begin next_state = s5; y_out = 1; end s5: begin next_state = s6; y_out = 1; end s6: begin next_state = s7; y_out = 1; end s7: begin next_state = s8; y_out = 1; end s8: begin next_state = s0; y_out = 1; end default: next_state = s0; endcase end endmodule // Test plan // Verify the following: // Power-up reset // Response to start in initial state // Reset on-the-fly // Response to re-assertion of start after reset on-the-fly // 8-cycle counting sequence // Ignore start during counting sequence // Return to initial state after 8 cycles and await start // Remain in initial state for one clock if start is asserted when the state is entered module t_Prob_6_45; wire y_out; reg start, clock, reset_bar; Prob_6_45 M0 (y_out, start, clock, reset_bar); initial #300 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork reset_bar = 0; #2 reset_bar = 1; #10 start = 1; #20 start = 0; #30 reset_bar = 0; #50 reset_bar = 1; #80 start = 1; #90 start = 0; #130 start = 1; #140 start = 0; #180 start = 1; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 214 0 Name 70 140 210 280 clock reset_bar start y_out 6.46 module Prob_6_46 (output reg [0: 3] timer, input clk, reset_b); always @ (negedge clk, negedge reset_b) if (reset_b == 0) timer <= 4'b1000; else case (timer) 4'b1000: timer <= 4'b0100; 4'b0100: timer <= 4'b0010; 4'b0010: timer <= 4'b0001; 4'b0001: timer <= 4'b1000; default: timer <= 4'b1000; endcase endmodule module t_Prob_6_46 (); wire [0: 3] timer; reg clk, reset_b; Prob_6_46 M0 (timer, clk, reset_b); initial #150 $finish; initial fork #1 reset_b = 0; #7 reset_b = 1; join initial begin clk = 1; forever #5 clk = ~clk; end endmodule Name 0 60 120 clk reset_b timer [0:3] 8 4 2 1 8 4 2 1 8 4 2 1 8 4 timer [0] timer [1] timer [2] timer [3] 6.47 module Prob_6_47 ( output reg P_odd, input D_in, CLK, reset ); wire D; assign D = D_in ^ P_odd; always @ (posedge CLK, posedge reset) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 215 if (reset) P_odd <= 0; else P_odd <= D; endmodule module t_Prob_6_47 (); wire P_odd; reg D_in, CLK, reset; Prob_6_47 M0 (P_odd, D_in, CLK, reset); initial #150 $finish; initial fork #1 reset = 1; #7 reset = 0; join initial begin CLK = 0; forever #5 CLK = ~CLK; end initial begin D_in = 1; forever #20 D_in = ~D_in; end endmodule Name 0 60 120 CLK reset D_in P_odd 6.48 (a) module Prob_6_48a (output reg [7: 0] count, input clk, reset_b); reg [3: 0] state; always @ (posedge clk, negedge reset_b) if (reset_b == 0) state <= 0; else state <= state + 1; always @ (state) case (state) 0, 2, 4, 6, 8, 10, 12: count = 8'b0000_0001; 1: count = 8'b0000_0010; 3: count = 8'b0000_0100; 5: count = 8'b0000_1000; 7: count = 8'b0001_0000; 9: count = 8'b0010_0000; 11: count = 8'b0100_0000; 13: count = 8'b1000_0000; default: count = 8'b0000_0000; endcase endmodule module t_Prob_6_48a (); wire [7: 0] count; reg clk, reset_b; Prob_6_48a M0 (count, clk, reset_b); initial #200 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial begin reset_b = 0; #2 reset_b = 1; end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 216 Name 0 60 120 180 clk reset_b state[3:0] 1 2 3 4 5 6 7 8 9 a b c d count[7:0] 02 01 04 01 08 01 10 01 20 01 40 01 80 e f 00 0 1 2 3 01 02 01 04 count[7] count[6] count[5] count[4] count[3] count[2] count[1] count[0] (b) module Prob_6_48b (output reg [7: 0] count, input clk, reset_b); reg [3: 0] state; always @ (posedge clk, negedge reset_b) if (reset_b == 0) state <= 0; else state <= state + 1; always @ (state) case (state) 0, 2, 4, 6, 8, 10, 12: count = 8'b1000_0000; 1: count = 8'b0100_0000; 3: count = 8'b0010_0000; 5: count = 8'b0001_0000; 7: count = 8'b0000_1000; 9: count = 8'b0000_0100; 11: count = 8'b0000_0010; 13: count = 8'b0000_0001; default: count = 8'b0000_0000; endcase endmodule module t_Prob_6_48b (); wire [7: 0] count; reg clk, reset_b; Prob_6_48b M0 (count, clk, reset_b); initial #180 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial begin reset_b = 0; #2 reset_b = 1; end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 217 Name 0 60 120 180 clk reset_b state[3:1] count[7:0] 0 40 1 80 2 20 80 3 10 80 4 08 80 5 04 80 6 02 80 7 01 00 0 80 count[7] count[6] count[5] count[4] count[3] count[2] count[1] count[0] 6.49 // Behavioral description of a 4-bit universal shift register // Fig. 6.7 and Table 6.3 module Shift_Register_4_beh ( // V2001, 2005 output reg [3: 0] A_par, // Register output input [3: 0] I_par, // Parallel input input s1, s0, // Select inputs MSB_in, LSB_in, // Serial inputs CLK, Clear // Clock and Clear ); always @ (posedge CLK, negedge Clear) // V2001, 2005 if (~Clear) A_par <= 4'b0000; else case ({s1, s0}) 2'b00: A_par <= A_par; // No change 2'b01: A_par <= {MSB_in, A_par[3: 1]}; // Shift right 2'b10: A_par <= {A_par[2: 0], LSB_in}; // Shift left 2'b11: A_par <= I_par; // Parallel load of input endcase endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 40 218 // Test plan: // test reset action load // test parallel load // test shift right // test shift left // test circulation of data // test reset on the fly module t_Shift_Register_4_beh (); reg s1, s0, // Select inputs MSB_in, LSB_in, // Serial inputs clk, reset_b; // Clock and Clear reg [3: 0] I_par; // Parallel input wire [3: 0] A_par; // Register output Shift_Register_4_beh M0 (A_par, I_par,s1, s0, MSB_in, LSB_in, clk, reset_b); initial #200 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork // test reset action load #3 reset_b = 1; #4 reset_b = 0; #9 reset_b = 1; // test parallel load #10 I_par = 4'hA; #10 {s1, s0} = 2'b11; // test shift right #30 MSB_in = 1'b0; #30 {s1, s0} = 2'b01; // test shift left #80 LSB_in = 1'b1; #80 {s1, s0} = 2'b10; // test circulation of data #130 {s1, s0} = 2'b11; #140 {s1, s0} = 2'b00; // test reset on the fly #150 reset_b = 1'b0; #160 reset_b = 1'b1; #160 {s1, s0} = 2'b11; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 219 0 Name 60 120 180 clk reset_b x I_par[3:0] a MSB_in LSB_in A_par[3:0] 0 a 5 2 1 0 1 3 7 f a 0 a s1 s0 Reset A_par Load_A_par Shift right 6.50 Shift left Load A_par No change Reset Load A_par (a) See problem 6.27. module Prob_8_50a (output reg [2: 0] count, input clk, reset_b); always @ (posedge clk, negedge reset_b) if (!reset_b) count <= 0; else case (count) 3'd0: count <= 3'd1; 3'd1: count <= 3'd2; 3'd2: count <= 3'd3; 3'd3: count <= 3'd4; 3'd4: count <= 3'd5; 3'd5: count <= 3'd6; 3'd4: count <= 3'd6; 3'd6: count <= 3'd0; default: count <= 3'd0; endcase endmodule module t_Prob_8_50a; wire [2: 0] count; reg clock, reset_b ; Prob_8_50a M0 (count, clock, reset_b); initial #130 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork reset_b = 0; #2 reset_b = 1; #40 reset_b = 0; #42 reset_b = 1; join endmodule Name 0 40 80 120 clock reset_b count[2:0] 0 1 2 3 4 0 1 2 3 4 5 6 0 1 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 2 220 (b) See problem 6.28. module Prob_8_50b (output reg [2: 0] count, input clk, reset_b); always @ (posedge clk, negedge reset_b) if (!reset_b) count <= 0; else case (count) 3'd0: count <= 3'd1; 3'd1: count <= 3'd2; 3'd2: count <= 3'd4; 3'd4: count <= 3'd6; 3'd6: count <= 3'd0; default: count <= 3'd0; endcase endmodule module t_Prob_8_50b; wire [2: 0] count; reg clock, reset_b ; Prob_8_50b M0 (count, clock, reset_b); initial #100 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork reset_b = 0; #2 reset_b = 1; #40 reset_b = 0; #42 reset_b = 1; join endmodule 0 30 60 90 reset_b clock count[2:0] 0 1 2 4 6 0 1 2 4 6 0 1 6.51 module Seq_Detector_Prob_5_51 (output detect, input bit_in, clk, reset_b); reg [2: 0] sample_reg; assign detect = (sample_reg == 3'b111); always @ (posedge clk, negedge reset_b) if (reset_b ==0) sample_reg <= 0; else sample_reg <= {bit_in, sample_reg [2: 1]}; endmodule module Seq_Detector_Prob_5_45 (output detect, input bit_in, clk, reset_b); parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3; reg [1: 0] state, next_state; assign detect = (state == S3); always @ (posedge clk, negedge reset_b) if (reset_b == 0) state <= S0; else state <= next_state; always @ (state, bit_in) begin next_state = S0; case (state) 0: if (bit_in) next_state = S1; else state = S0; 1: if (bit_in) next_state = S2; else next_state = S0; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 221 2: if (bit_in) next_state = S3; else state = S0; 3: if (bit_in) next_state = S3; else next_state = S0; default: next_state = S0; endcase end endmodule module t_Seq_Detector_Prob_6_51 (); wire detect_45, detect_51; reg bit_in, clk, reset_b; Seq_Detector_Prob_5_51 M0 (detect_51, bit_in, clk, reset_b); Seq_Detector_Prob_5_45 M1 (detect_45, bit_in, clk, reset_b); initial #350$finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork reset_b = 0; #4 reset_b = 1; #10 bit_in = 1; #20 bit_in = 0; #30 bit_in = 1; #50 bit_in = 0; #60 bit_in = 1; #100 bit_in = 0; join endmodule Name 0 60 120 clk reset_b bit_in detect_51 detect_45 The circuit using a shift register uses less hardware. 6.52 Universal Shift Register module Prob_6_52 ( output [3:0] A_par, input [3: 0] In_par, input MSB_in, LSB_in, input [1: 0] s1, s0, input CLK, Clear_b ); wire y0, y1, y2, y3; Mux_4x1 M0 (y0, In_par[0], LSB_in, A_par[1], A_par[0], s1, s0); Mux_4x1 M1 (y1, In_par[1], A_par[0], A_par[2], A_par[1], s1, s0); Mux_4x1 M2 (y2, In_par[2], A_par[1], A_par[3], A_par[2], s1, s0); Mux_4x1 M3 (y3, In_par[3], A_par[2], MSB_in, A_par[3], s1, s0); DFF D0 (A_par[0], y0, CLK, Clear_b); DFF D1 (A_par[1], y1, CLK, Clear_b); DFF D2 (A_par[2], y2, CLK, Clear_b); DFF D3 (A_par[3], y3, CLK, Clear_b); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 222 module Mux_4x1 (output reg y, input in3, in2, in1, in0, s1, s0); always @ (in3, in2, in1, in0, s1, s0) case ({s1, s0}) 2'b00: y = in0; 2'b01: y = in1; 2'b10: y = in2; 2'b11: y = in3; endcase endmodule module DFF (output reg q, input d, clk, clr_b); always @ (posedge clk, negedge clr_b) if (clr_b == 1'b0) q <= 0; else q <= d; endmodule Features to be tested: Action of Clear_b Power-up initialization On-the-fly Action of mode controls s1 s0 0 0 No change 0 1 Shift right 1 0 Shift left 1 1 Parallel load module t_Problem_6_52 (); wire [3:0] A_par; reg [3: 0] In_par; reg MSB_in, LSB_in; reg s1, s0; reg CLK, Clear_b; reg [3:0] In_par; Prob_6_52 M0 (A_par, In_par, MSB_in, LSB_in, s1, s0, CLK, Clear_b); initial #300 $finish; initial begin CLK = 0, forever #5 CLK = ~CLK; end initial fork Clear_b = 0; // Power-up initialization #20 Clear_b = 1; // Running In_par = 4'b1010; MSB_in = 1'b1; LSB_in = 1'b0; s1 = 0; s0 = 0; #40 begin s1 = 1; s0 = 1; end #60 Clear_b = 1'b0; #80 Clear_b = 1'b1; #90 begin s1 = 0; s0 = 0; end // Word for parallel load // Bit for serial load // Bit for serial load // Initial action to no change // parallel load // Reset on-the-fly // Resume action with parallel load at next clock edge // No action – register holds 4'b1010 #120 Clear_b = 1'b0; // Clear register #130 Clear_b = 1'b1; #140 begin s1 = 1'b0; s0 = 1'b1; end // Shifting to right (from MSB) #170 begin s1 = 1'b0; s0 = 1'b0; end // Register should hold 4'b1111 #190 begin Clear_b = 1'b0; s1 = 1'b0; s0 = 1'b0; end #200 begin Clear_b = 1'b1; s1 = 1'b1; s0 = 1'b0; end #230 begin s1 = 1'b0; s0 = 1'b0; end join endmodule // Resume action – shift left Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 223 6.53 module Prob_6_53 (output reg [3:0] SR_A, input Shift_control, SI, CLK, Clear_b); reg [3: 0] SR_B; wire Sum, Carry; wire SO_A = SR_A[3]; wire SO_B = SR_B[3]; wire SI_A = Sum; wire SI_B = SI; wire Q; always @ (posedge CLK) if (Clear_b == 1'b0) SR_A<= 4'b0; else if (Shift_control) SR_A <= {Sum, SR_A[3:1]}; always @ (posedge CLK) if (Clear_b == 1'b0) SR_B <= 4'b0; else if (Shift_control) SR_B <= {SI, SR_B[3:1]}; FA M0 (Sum, Carry, SO_A, SO_B, Q); and (clk_to_DFF, CLK, Shift_control); // Caution: gated clock DFF M1 (Q, Carry, clk_to_DFF, Clear_b); endmodule module FA (output S, C, input x, y, z); assign {C, S} = x + y + z; endmodule module DFF (output reg Q, input D, C, Clear_b); always @ (posedge C) if (Clear_b == 1'b0) Q <= 1'b0; else Q <= D; endmodule module t_Prob_6_53 (); wire [3:0] SR_A; reg Shift_control, SI, CLK, Clear_b; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 224 Prob_6_53 M0 (SR_A, Shift_control, SI, CLK, Clear_b); initial #300 $finish; initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork Clear_b = 0; #20 Clear_b = 1; #40 Shift_control = 1; SI = 0; // Sequence of 1s /* #60 SI = 1; #70 SI = 0; #100 SI = 1; #110 SI = 0; #140 SI = 1; #150 SI = 0; #180 SI = 1; #190 SI = 0; */ // Sequence of threes #60 SI = 1; #80 SI = 0; #100 SI = 1; #120 SI = 0; #140 SI = 1; #160 SI = 0; #180 SI = 1; #200 SI = 0; join endmodule Simulation results for accumulating a sequence of four 1s. Sequence of four 1s Accumulation of 1s Simulation results for accumulating a sequence of four 3s. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 225 Sequence of four 3s Accumulation of 3s Additional test patterns are left to the student. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 226 6.54 module Prob_6_54 (output reg [3:0] SR_A, input Shift_control, SI, CLK, Clear_b); reg [3:0] SR_B; wire S; wire Q; wire SI_A = S; wire SO_A = SR_A[0]; wire SO_B = SR_B[0]; wire SI_B = SI; and (J_in, SO_A, SO_B); nor (K_in, SO_A, SO_B); xor (S, SO_A, SO_B, Q); and (clk_to_JKFF, Shift_control, CLK); always @ (posedge CLK) if (Clear_b == 1'b0) SR_A<= 4'b0; else if (Shift_control) SR_A <= {SI_A, SR_A[3:1]}; always @ (posedge CLK) if (Clear_b == 1'b0) SR_B <= 4'b0; else if (Shift_control) SR_B <= {SI_B, SR_B[3:1]}; and (clk_to_JKFF, CLK, Shift_control); // Caution: gated clock JKFF M1 (Q, J_in, K_in, clk_to_JKFF, Clear_b); endmodule module FA (output S, C, input x, y, z); assign {C, S} = x + y + z; endmodule module JKFF (output reg Q, input J_in, K_in, C, Clear_b); always @ (posedge C) if (Clear_b == 1'b0) Q <= 1'b0; else case ({J_in, K_in}) 2'b00: Q <= Q; 2'b01: Q <= 1'b0; 2'b10: Q <= 1'b1; 2'b11: Q <= ~Q; endcase endmodule module t_Prob_6_54 (); wire [3:0] SR_A; reg Shift_control, SI, CLK, Clear_b; Prob_6_54 M0 (SR_A, Shift_control, SI, CLK, Clear_b); //initial #200 $finish; // sequence of 1s initial #400 $finish; // sequence of 3s initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork Clear_b = 0; #20 Clear_b = 1; #40 Shift_control = 1; SI = 0; // Sequence of 1s /* #60 SI = 1; #70 SI = 0; #100 SI = 1; #110 SI = 0; #140 SI = 1; #150 SI = 0; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 227 #180 SI = 1; #190 SI = 0; */ // Sequence of threes #60 SI = 1; #80 SI = 0; #100 SI = 1; #120 SI = 0; #140 SI = 1; #160 SI = 0; #180 SI = 1; #200 SI = 0; join endmodule Simulation results: Accumulation of a sequence of four 1s. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 228 Sequence of four 1s Accumulation of 1s Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 229 Accumulation of a sequence of 3s: Accumulation of 3s Sequence of three 3s Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 230 6.55 module Prob_6_55 (output Q8, Q4, Q2, Q1, input Count, Clear_b); supply1 Pwr; not (Q8_bar, Q8); and (J_in_M8, Q2, Q4); JKFF M1 (Q1, Pwr, Pwr, Count, Clear_b); JKFF M2 (Q2, Q8_bar, Pwr, Q1, Clear_b); JKFF M4 (Q4, Pwr, Pwr, Q2_ Clear_b); JKFF M8 (Q8, J_in_M8, Pwr, Q1_ Clear_b); endmodule module JKFF (output reg Q, input J_in, K_in, C, Clear_b); always @ (negedge C) if (Clear_b== 1'b0) Q <= 1'b0; else case ({J_in, K_in}) 2'b00: Q <= Q; 2'b01: Q <= 1'b0; 2'b10: Q <= 1'b1; 2'b11: Q <= ~Q; endcase endmodule module t_Prob_6_55 (); wire Q8, Q4, Q2, Q1; reg Count , Clear_b; wire [3:0] value = {Q8, Q4, Q2, Q1}; // Display counter Prob_6_55 M0 (Q8, Q4, Q2, Q1, Count, Clear_b); initial #200 $finish; initial begin Count = 0; forever #5 Count = ~Count ; end initial fork Clear_b = 0; #20 Clear_b = 1; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 6.56 231 Clear_b module Prob_6_56 (output A3, A2, A1, A0, Next_stage, input Count_enable, CLK, Clear_b); assign Next_stage = A3 && A2 && A1 && A0; and (JK_in_M1, Count_enable, A0); and (JK_in_M2, JK_in_M1, A1); and (JK_in_M3, JK_in_M2, A2); and (Next_stage, JK_in_M3, A3); JKFF M0 (A0, Count_enable, Count_enable, CLK, Clear_b); JKFF M1 (A1, JK_in_M1, J_in_M1, CLK, Clear_b); JKFF M2 (A2, JK_in_M2, JK_in_M2, CLK, Clear_b); JKFF M3 (A3, JK_in_M3, JK_in_M3, A3, CLK, Clear_b); endmodule module JKFF (output reg Q, input J_in, K_in, C, Clear_b); always @ (posedge C) if (Clear_b == 1'b0) Q <= 0; else case ({J_in, K_in}) 2'b00: Q <= Q; 2'b01: Q <= 1'b0; 2'b10: Q <= 1'b1; 2'b11: Q <= ~Q; endcase endmodule module t_Prob_6_56 (); wire A3, A2, A1, A0; wire Next_stage; reg Count_enable; reg CLK, Clear_b wire [3:0] value = {A3, A2, A1, A0}; Prob_6_56 M0 (A3, A2, A1, A0, Next_stage, Count_enable, CLK, Clear_b); initial #400 $finish; initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork Clear_b = 0; #10 Clear_b = 1; #100 Clear_b = 0; // Reset on the fly #120 Clear_b = 1; Count_enable = 0; #20 Count_enable = 1; #50 Count_enable = 0; #80 Count_enable = 1; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 232 233 6.57 module Prob_6_57 (output A3, A2, A1, A0, input Up, Down, CLK, Clear_b); not (Up_bar, Up); not (A0_bar, A0); not (A1_bar, A1); not (A2_bar, A2); and (w1, Up_bar, Down); and (w2, w1, A0_bar); and (w3, Up, A0); and (w4, w2, A1_bar); and (w5, w3, A1); and (w6, w4, A2_bar); and (w7, w5, A2); or (T0, w1, Up); or (T1, w2, w3); or (T2, w4, w5); or (T3, w6, w7); TFF M0 (A0, A0_bar, T0, CLK, Clear_b); TFF M1 (A1, A1_bar, T1, CLK, Clear_b); TFF M2 (A2, A2_bar, T2, CLK, Clear_b); TFF M3 (A3, A3_bar, T3, CLK, Clear_b); endmodule module TFF (output reg Q, output Q_bar, input T, Clear_b, C, Clear_b); // Active low reset is needed assign Q_bar = ~Q; always @ (posedge C) if (Clear_b == 1'b0) Q <= 0; else if (T) Q <= ~Q; endmodule module t_Prob_6_57 (); wire A3, A2, A1, A0; reg Up, Down, CLK, Clear_b; wire [3:0] value = {A3, A2, A1, A0}; // Display count Prob_6_57 M0(A3, A2, A1, A0, Up, Down, CLK, Clear_b); initial #250 $finish; initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork Clear_b = 1'b0; #20 Clear_b = 1'b1; #60 Clear_b = 0; // Reset on the fly #80 Clear_b = 1; Up = 1'b0; Down = 1'b0; #50 Up = 1'b1; #80 Down = 1'b1; #160 Up = 1'b0; #200 Down = 1'b0; join endmodule // Up has priority Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 234 235 6.58 module Problem_6_58 (output A3, A2, A1, A0, C_out, input I3, I2, I1, I0, Count, Load, CLK, Clear_b); not (Load_bar, Load); not (I0_bar, I0); not (I1_bar, I1); not (I2_bar, I2); not (I3_bar, I3); and (w0, Count, Load_bar); and (w1, Load, I0); and (w2, Load, I0_bar); and (w3, Load, I1); and (w4, Load, I1_bar); and (w5, Load, I2); and (w6, Load, I2_bar); and (w7, Load, I3); and (w8, Load, I3_bar); or ( w9, w1, w0); or ( w10, w2, w0); or ( w11, w3, w17); or ( w12, w4, w17); or ( w13, w5, w18); or ( w14, w6, w18); or ( w15, w7, w19); or ( w16, w8, w19); and (w17, w0, A0); and (w18, w0, A0, A1); and (w19, w0, A0, A1, A2); and (C_out, w0, A0, A1, A2, A3); JKFF M0 (A0, w9, w10, CLK, Clear_b); JKFF M1 (A1, w11, w12, CLK, Clear_b); JKFF M2 (A2, w13, w14, CLK, Clear_b); JKFF M3 (A3, w15, w16, CLK, Clear_b); endmodule module JKFF (output reg Q, input J_in, K_in, C, Clear_b); always @ (posedge C) if (Clear_b == 1'b0) Q <= 0; else case ({J_in, K_in}) 2'b00: Q <= Q; 2'b01: Q <= 1'b0; 2'b10: Q <= 1'b1; 2'b11: Q <= ~Q; endcase endmodule module t_Problem_6_58 (); wire A3, A2, A1, A0, C_out; reg I3, I2, I1, I0, Count, Load, CLK, Clear_b; wire [3:0] value = {A3, A2, A1, A0}; wire [3:0] Par_word = {I3, I2, I1, I0}; Problem_6_58 M0 (A3, A2, A1, A0, C_out, I3, I2, I1, I0, Count, Load, CLK, Clear_b); initial #400 $finish; initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork {I3, I2, I1, I0} = 4'b0101; // Data for parallel load Clear_b = 0; #20 Clear_b = 1; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Count = 0; #50 Count = 1; // Counting #150 Count = 0; // Pause #200 Count = 1; // Resume counting Load = 0; #250 Load = 1; // Parallel load #260 Load = 0; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 236 237 6.59 module Problem_6_59 (output reg A3, A2, A1, A0, output C_out, input I3, I2, I1, I0, Count, Load, CLK, Clear_b); always @ (posedge CLK) if (Clear_b == 1'b0) {A3, A2, A1, A0} <= 4'b0; else if (Load) {A3, A2, A1, A0} <= {I3, I2, I1, I0}; else if (Count) {A3, A2, A1, A0} <= {A3, A2, A1, A0} + 4'b0001; assign C_out = A3 && A2 && A1 && A0 && Count && (!Load); endmodule module t_Problem_6_59 (); wire A3, A2, A1, A0, C_out; reg I3, I2, I1, I0, Count, Load, CLK, Clear_b; wire [3:0] value = {A3, A2, A1, A0}; wire [3:0] Par_word = {I3, I2, I1, I0}; Problem_6_59 M0 (A3, A2, A1, A0, C_out, I3, I2, I1, I0, Count, Load, CLK, Clear_b); initial #400 $finish; initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork {I3, I2, I1, I0} = 4'b0101; // Data for parallel load Clear_b = 0; #20 Clear_b = 1; Count = 0; #50 Count = 1; // Counting #150 Count = 0; // Pause #200 Count = 1; // Resume counting Load = 0; #250 Load = 1; // Parallel load #260 Load = 0; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 238 239 Chapter 7 7.1 mdc 1/19/07 11:02 AM (a) 8 K x 32 = 213 x 16 A = 13 D = 16 (b) 2 G x 8 = 231 x 8 A = 31 D=8 (c) 16 M x 32 = 224 x 32 A = 24 D = 32 (d) 256 K x 64 = 218 x 64 A = 18 Comment [1]: Spell check D = 64 (e) 7.2 (a) 213 (b) 231 (c) 226 (d) 221 7.3 Address: 56310 = 10_0011_00112 Data word: 1,21210 = 0000_0100_1011_11002 7.4 f CPU = 150 MHz, TCPU = 1/fCPU = 6.67-9 Hz-1 15 ns 6.67 ns CPU clock Address T1 6.67 ns T2 6.67 ns T3 Address valid Memory select Data from CPU Data valid for write Data from memory Data valid for read 7.5 Pending Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 240 7.6 8 Data input lines 8 4 4 R/W 3 A0 A1 3 4 x 4 RAM A'2 A2 4 x 4 RAM A'2 E E 4 4 4 4 3 3 4 x 4 RAM A2 4 x 4 RAM A2 E 4 E 4 8 8 Data output lines Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 7.7 241 (a) 16 K = 214 = 27 x 27 = 128 x 128 Each decoder is 7 × 128 Decoders require 256 AND gates, each with 7 inputs (b) 6,000 = 0101110_1110000 x = 46 y = 112 7.8 (a) 256 K / 32 K = 8 chips (b) 256 K = 218 (18 address lines for memory); 32 K = 215 (15 address pins / chip) (c) 18 – 15 = 3 lines ; must decode with 3 × 8 decoder 7.9 13 + 12 = 25 address lines. Memory capacity = 225 words. 7.10 01011011 = 1 2 3 4 5 6 7 8 9 10 11 12 13 P1 P2 0 P4 1 0 1 P8 1 0 1 1 P13 P1 = Xor of bits (3, 5, 7, 9, 11) = 0, 1, 1, 1, 1 = 0 P2 = Xor of bits (3, 6, 7, 10, 11) = 0, 0, 1, 0, 1 = 0 P4 = Xor of bits (5, 6, 7, 12) = 1, 0, 1, 1 = 1 P8= Xor of bits (9, 10, 11, 12) = 1, 0, 1, 1, = 1 (Note: even # of 0s) (Note: odd # of 0s) Composite 13-bit code word: 0001 1011 1011 1 7.11 11001001010 = 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P1 P2 1 P4 1 0 0 P8 1 0 0 1 0 1 0 P1 = Xor of bits (3, 5, 7, 9, 11, 13, 15) = 1, 1, 0, 1, 0, 0, 0 = 1 P2 = Xor of bits (3, 6, 7, 10, 11, 14, 15) = 1, 0, 0, 0, 0, 1, 0 = 0 P4 = Xor of bits (5, 6, 7, 12, 13, 14, 15) = 1, 0, 0, 1, 0, 1, 0 = 1 P8= Xor of bits (9, 10, 11, 12, 13, 14, 15) = 1, 0, 0, 1, 0, 1, 0 = 1 (Note: odd # of 0s) (Note: even # of 0s) Composite 15-bit code word: 101 110 011 001 010 7.12 (a) 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 1 1 1 0 1 0 1 0 C1 (1, 3, 5, 7, 9, 11) = 0, 0, 1, 1, 1, 1 = 0 C2 (2, 3, 6, 7, 10, 11) = 0, 0, 1, 1, 0, 1 = 1 C4 (4, 5, 6, 7, 12) = 0, 1, 1, 1, 0 = 1 C8 (8, 9, 10, 11, 12) = 0, 1, 0, 1, 0 = 0 C = 0110 Error in bit 6. Correct data: 0101 1010 (b) 1 2 3 4 5 6 7 8 9 10 11 12 1 0 1 1 1 0 0 0 0 1 1 0 C1 (1, 3, 5, 7, 9, 11) = 1, 1, 1, 0, 0, 1 = 0 C2 (2, 3, 6, 7, 10, 11) = 0, 1, 0, 0, 1, 1 = 1 C4 (4, 5, 6, 7, 12) = 1, 1, 0, 0, 0 = 0 C8 (8, 9, 10, 11, 12) = 0, 0, 1, 1, 0 = 0 C = 0010 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 242 Error in bit 2 = Parity bit P2. Correct 8-bit data: 3 5 6 7 9 10 11 12 1 1 0 0 0 1 1 0 (c) 1 2 3 4 5 6 7 8 9 10 11 12 1 0 1 1 1 1 1 1 0 1 0 0 C = 0000 )No errors) C1 (1, 3, 5, 7, 9, 11) = 1, 1, 1, 0, 0, 1 = 0 C2 (2, 3, 6, 7, 10, 11) = 0, 1, 0, 0, 1, 1 = 1 C4 (4, 5, 6, 7, 12) = 1, 1, 0, 0, 0 = 0 C8 (8, 9, 10, 11, 12) = 0, 0, 1, 1, 0 = 0 Correct 8-bit data: 7.13 7.14 3 5 6 7 9 10 11 12 1 1 1 1 0 1 0 0 (a) 16-bit data (From Table 7.2): 5 Check bits 1 bit ---------------6 parity bits (b) 32-bit data (From Table 7.2): 6 Check bits 1 bit ---------------7 parity bits (6) 16-bit data (From Table 7.2): 5 Check bits 1 bit ---------------6 parity bits (a) 1 2 3 4 5 6 7 P1 P2 0 P4 0 1 0 P1 = Xor (3, 5, 7) = 0, 0, 0 = 1 P2 = Xor (3, 6, 7) = 0, 1, 0 = 0 P4 = Xor (5, 6, 7) = 0, 1, 0 = 1 7-bit word: 0101010 (b) No error: C1 = Xor (1, 3, 5, 7) = 0, 0, 0, 0 = 0 C2 = Xor (2, 3, 6, 7) = 1, 0, 1, 0 = 0 C4 = Xor (4, 5, 6, 7) = 1, 0, 1, 0 = 0 (c) Error in bit 5: 1 2 3 4 5 6 7 0 1 0 1 1 1 0 C1 = Xor (0, 0, 1, 0) = 1 C2 = Xor (1, 0, 1, 0) = 0 C4 = Xor (1, 1, 1, 0) = 1 Error in bit 5: C = 101 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 243 (d) 8-bit word 1 2 3 4 5 6 7 8 0 1 0 1 0 1 0 1 Error in bits 2 and 5: 0 0 0 1 1 1 0 1 C1 = Xor (0, 0, 1, 0) = 1 C2 = Xor (0, 0, 1, 0) = 1 C4 = Xor (1, 1, 1, 0) = 1 P=0 C =(1, 1, 1) ≠ 0 and P = 0 indicates double error. 7.15 6 Address (9 bits) 6 6 6 6 64 x 8 ROM 64 x 8 ROM 64 x 8 ROM 64 x 8 ROM 3 x8 Decoder En Note: Outputs must be wired-OR or three-state outputs. Data (8 bits) En 8 En 8 En 64 x 8 ROM En 8 En 8 En 64 x 8 ROM 8 8 En 64 x 8 ROM 64 x 8 ROM 8 Note: Outputs must be wired-OR or three-state outputs. 7.16 Note: 4096 = 212 Pwr Gnd Inputs 12 4096 x 8 ROM 8 Outputs CS 7.18 (a) 256 × 8 6 16 inputs + 8 outputs requires a 24-pin IC. (b) 512 × 5 (c) 1024 × 4 (d) 32 × 7 7.17 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 8 244 Input Address 7.18 Output of ROM I5 I4 I3 I 2 I 1 D6D5D4 D3D2D1 00000 00001 … … 01000 01001 … … 11110 11111 000 000 … … 001 001 … … 110 110 000 001 … … 011 100 … … 000 001 (a) 8 inputs 8 outputs 28 x 8 256 x 8 ROM (b) 9 inputs 5 outputs 29 x 5 512 x 5 ROM (c) 10 inputs 4 outputs 210 x 4 1024 x 4 ROM (d) 5 inputs 25 x 7 7 outputs D0 (20) Decimal 0, 1 0, 1 … … 0, 1 0, 1 … … 0, 1 0, 1 0, 1 2, 3 … … 16, 17 18, 19 … … 60, 61 62, 63 32 x 7 ROM Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 245 7.19 x y yz 00 m0 0 m4 x 01 1 11 m1 0 1 00 0 m6 0 01 m0 0 m7 y yz m2 1 m5 0 10 m3 1 x x 1 0 m0 0 0 m4 x 1 m1 0 11 m3 0 m5 x 10 0 0 m6 0 Product Inputs term x y z 1 2 3 4 5 6 7 8 9 10 11 00 -01 0-1 110 1100011 101 101–1 -01 010 01 m0 m1 0 0 x 1 11 m3 1 m4 z C = x'yz + xy'z C' = z' + x'y' + xy y'z x'z xyz' xy x'y' x'yz xy'z xy' Xz y'z x'yz' 1 y yz m2 1 m7 1 1 B = xy + x'y' B' = xy' + x'y y 01 m6 z yz 00 0 m7 z A = y'z + x'z + xyz' A' =y'z' + x'z' + xyz x m2 0 m5 0 10 m3 1 m4 1 11 m1 1 m5 1 0 m7 1 10 m2 1 m6 1 0 z D = xy' + xz + y'z + x'yz' D' = x'y'z' + x'yz + xyz' Outputs A B C D 1 1 1 - 1 1 - 1 1 - 1 1 1 1 1 7.20 Inputs xyz 000 001 010 011 100 101 110 111 Outputs A, B, C, D 1101 0111 0000 1001 1100 0011 1000 0101 M[001] = 0111 M[100] = 1100 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 246 7.21 Note: See truth table in Fig. 7.12(b). A2 00 0 A2 A1 A1A0 1 m0 m4 01 m1 0 m5 0 11 m3 0 m7 0 A2 10 m2 0 m6 1 0 00 0 1 A2 A1 A1A0 1 m0 m4 0 01 m1 m5 1 0 1 A0 0 A2 1 m0 m4 01 m1 0 m5 0 11 m3 0 m7 1 m6 1 0 0 F2 = A2A'1 + A2A0 F2' = A'2 + A1A'0 A1 A1A0 00 m7 10 m2 0 A0 F1 = A2A1 F'1 = A'2 + A'1 A2 11 m3 A2 10 m2 1 m6 0 0 00 0 0 A2 A1 A1A0 1 m0 m4 A0 0 0 01 m1 m5 0 0 11 m3 m7 0 0 10 m2 m6 1 1 A0 F3 = A'2A1A0 + A2A'1A0 F3' = A'0 + A'2A'1 +A2A1 F4 = A1A'0 F'4 = A'1 + A0 Product Inputs Outputs term A2A1A0 F1 F2 F3 F4 A2A1 A'2 A1A'0 A'2A1A0 A2A'1 1 2 3 4 5 1 0 1 1 1 1 0 0 1 1 1 T 1 1 C 1 1 T 1 T Alternative: F'1, F'2, F3, F4 (5 terms) 7.22 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 4 9 16 25 36 49 64 81 100 121 144 169 196 225 w x y z b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note: b0 = z, and b1 = 0. ROM would have 4 inputs and 6 outputs. A 4 x 8 ROM would waste two outputs. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 247 wx 00 00 01 11 w 10 wx 01 m3 m2 m4 m5 m7 m6 m12 m13 m15 m14 m8 m9 m11 m10 11 w 10 yz m0 m4 1 01 11 w 10 m5 1 m3 m7 w 10 1 m9 m11 m10 x 11 w 10 z b4 = w'xz + xy'z' + wx' z y m0 01 m1 11 m3 m2 m4 m5 m7 m12 m13 m15 m14 m8 m9 m11 m10 1 1 wx 10 1 1 z b6 = wy + wx' 1 m5 m12 m8 x 11 w 10 11 m3 1 10 m2 m7 m6 m13 m15 m14 m9 m11 m10 1 1 1 x z b3 = xy'z + x' yz y 01 11 10 m0 m1 m3 m4 m5 m7 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 1 m2 m6 1 x 1 z b5 = w'xy + wxz + wx'y y 00 01 1 m1 m4 yz 00 m6 m0 00 01 m8 01 yz 00 m6 m14 1 wx m2 m15 1 11 10 m13 1 x y 11 00 01 1 y yz 00 1 m12 00 00 m1 1 1 z b2 = yx' 01 wx 10 m1 00 01 11 m0 yz 00 wx y yz m0 m4 01 m1 m5 11 m3 m7 10 m2 m6 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 x 1 z b7 = wx Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 248 7.23 Product Inputs term A B C D From Fig. 4-3: w = A + BC + BD w' = A'B' + A'C'D' x = B'C + B'D + BC'D' x' = B'C'D' + BC BD y = CD + C'D' y' = C'D + CD' z = D' z' = D Use w, x', y, z (7 terms) A BC BD B'C'D' CD C'D' D' 1 2 3 4 5 6 7 1 - 1 1 0 - 1 0 1 0 - Outputs F1 F2 F3 F4 1 0 1 0 0 1 1 1 - 1 1 1 - 1 1 - 1 T C T T 7.24 AND Product Inputs term A B C D 1 2 3 4 5 6 7 8 9 10 11 12 1 - 1 1 0 0 1 - 1 1 0 1 0 - 1 1 0 1 0 0 - Outputs w = A + BC + BD x = B'C + B'D + BC'D' y = CD + C'D' z = D' Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 249 7.25 x y yz 00 01 m0 0 m1 0 1 x x 1 m7 0 m6 1 0 z 01 11 m1 0 m3 1 m4 1 m7 0 1 0 0 m4 1 x 1 m1 m3 1 m5 0 11 1 m7 1 10 m2 1 m6 1 0 z D = z + x'y Outputs A = yz' + xz' + x'y'z B = y'z' + x'y' + yz C = A + xyz 1 - m0 01 0 0 1 0 1 1 1 - 00 m2 z C = A + xyz 1 0 0 0 1 1 1 - y yz m6 1 AND Product Inputs term x y z A x 10 0 m5 1 0 0 0 0 1 0 0 0 - 0 B = y'z' + x'y' + yz y 1 2 3 4 5 6 7 8 9 10 11 12 m2 1 m5 1 10 m3 1 z 00 1 11 m1 1 m4 1 01 A = yz' + xz' + x'y'z m0 x 0 m6 0 yz 0 00 m0 1 m7 0 y yz m2 0 m5 1 x 10 m3 1 m4 x 11 D = z + x'y A = yzʹ′ + xzʹ′ + xʹ′yʹ′z B = y'z' + x'y' + yz C = A + xyz D = z + xʹ′y Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 250 x x' y y' z z' A B C D Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 251 7.26 x x' y A y' A' CLK OE = 1 D SET CLR A Q Q x y 7.27 The results of Prob. 6.17 can be used to develop the equations for a three-bit binary counter with D-type flip-flops. DA0 = A'0 DA1 = A'1A0 + A1A'0 DA2 = A'2 A1A0 + A2A'1 + A2A'0 Cout = A2A1A0 Cout 0 1 2 3 4 5 6 7 8 9 A0 A1 A2 10 11 12 13 14 15 D SET CLR Q A0 Q clock D SET CLR Q A1 Q clock D SET CLR clock Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Q Q A2 252 7.28 A B C A'B AC A'BC' AC AB BC F'2 F1 7.29 Product term x'y'A 1 x'yA' 2 xy'A' 3 xyA 4 Inputs xyA 001 010 100 111 Output DA 1 1 1 1 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 253 CHAPTER 8 8.1 8.2 (a) The transfer and increment occur concurrently, i.e., at the same clock edge. After the transfer, R2 holds the contents that were in R1 before the clock edge, and R2 holds its previous value incremented by 1. (b) Decrement the content of R3 by one. (c) If (S1 = 1), transfer content of R1 to R0. If (S1 = 0 and S2 = 1), transfer content of R2 to R0. S1 clr_R reset_b x y x y 0 ... incr_R R 1 clr_R reset_b clock 1 y R <= 0 1 Controller Datapath R <= R + 1 incr_R S3 S2 8.3 reset_b reset_b S1 S1 x S1 1 x 1 1 add_by_2 reset_b S2 x S3 y S2 1 S2 R <= R + 2 S3 (a) (c) (b) 8.4 1 1 z 011 010 y 1 0 z x 1 y 1 z z 1 1 111 110 001 110 000 100 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 254 8.5 The operations specified in a flowchart are executed sequentially, one at a time. The operations specified in an ASM chart are executed concurrently for each ASM block. Thus, the operations listed within a state box, the operations specified by a conditional box, and the transfer to the next state in each ASM block are executed at the same clock edge. For example, in Fig. 8.5 with Start = 1 and Flag = 1, signal Flush_R is asserted. At the clock edge the state moves to S_2, and register R is flushed. An ASM chart describes the state transitions and output signals generated by a finite state machine in response to its input signals. An ASMD chart is an ASM chart that has been annotated to indicate the register operations that are executed by the machine in response to the control signals (outpus) generated by the state machine. 8.6 Note: In practice, the asynchronous inputs x and y should be synchronized to the clock to avoid metastable conditons in the flip-flops.. count <= 0 reset_b count <= count - 1 decr count <= count + 1 S_idle incr 11 01 10 {y, x} 00 S_out 01 S_in 00 {y, x} 11 10 00 01 S_in_out 00 10 decr {y, x} decr incr incr S_in 11 incr 01 11 10 {y, x} x y Controller decr Datapath count ... reset_b clock S_out S_idle Note: To avoid counting a person more than once, the machine waits until x or y is deasserted before incrementing or decrementing the counter. The machine also accounts for persons entering and leaving simultaneously. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 255 8.7 RTL notation: S0: Initial state: if (start = 1) then (RA ← data_A, RB ← data_B, go to S1). S1: {Carry, RA} ← RA + (2's complement of RB), go to S2. S2: If (borrow = 0) go to S0. If (borrow = 1) then RA ← (2's complement of RA), go to S0. Block diagram and ASMD chart: reset_b data_A data_B borrow 8 Load_A_B start done Controller Subtract Convert carry reset_b clock S0 done 8 Datapath Reg_A ... Reg_B ... result ... 8 result start 1 Reg_A <= data_A Reg_B <= data_B Load_A_B S1 Subtract Reg_A <= Reg_A + ~ Reg_B + 1 S2 borrow Reg_A <= ~Reg_A + 1 1 Convert module Subtractor_P8_7 (output done, output [7:0] result, input [7: 0] data_A, data_B, input start, clock, reset_b); Controller_P8_7 M0 (Load_A_B, Subtract, Convert, done, start, borrow, clock, reset_b); Datapath_P8_7 M1 (result, borrow, data_A, data_B, Load_A_B, Subtract, Convert, clock, reset_b); endmodule module Controller_P8_7 (output reg Load_A_B, Subtract, output reg Convert, output done, input start, borrow, clock, reset_b); parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10; reg [1: 0] state, next_state; assign done = (state == S0); always @ (posedge clock, negedge reset_b) if (!reset_b) state <= S0; else state <= next_state; always @ (state, start, borrow) begin Load_A_B = 0; Subtract = 0; Convert = 0; case (state) S0: if (start) begin Load_A_B = 1; next_state = S1; end S1: begin Subtract = 1; next_state = S2; end S2: begin next_state = S0; if (borrow) Convert = 1; end default: next_state = S0; endcase end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 256 module Datapath_P8_7 (output [7: 0] result, output borrow, input [7: 0] data_A, data_B, input Load_A_B, Subtract, Convert, clock, reset_b); reg carry; reg [8:0] diff; reg [7: 0] RA, RB; assign borrow = carry; assign result = RA; always @ (posedge clock, negedge reset_b) if (!reset_b) begin carry <= 1'b0; RA <= 8'b0000_0000; RB <= 8'b0000_0000; end else begin if (Load_A_B) begin RA <= data_A; RB <= data_B; end else if (Subtract) {carry, RA} <= RA + ~RB + 1; // In the statement above, the math of the LHS is done to the wordlength of the LHS // The statement below is more explicit about how the math for subtraction is done: // else if (Subtract) {carry, RA} <= {1'b0, RA} + {1'b1, ~RB } + 9'b0000_0001; // If the 9-th bit is not considered, the 2s complement operation will generate a carry bit, // and borrow must be formed as borrow = ~carry. else if (Convert) RA <= ~RA + 8'b0000_0001; end endmodule // Test plan – Verify; // Power-up reset // Subtraction with data_A > data_B // Subtraction with data_A < data_B // Subtraction with data_A = data_B // Reset on-the-fly: left as an exercise module t_Subtractor_P8_7; wire done; wire [7:0] result; reg [7: 0] data_A, data_B; reg start, clock, reset_b; Subtractor_P8_7 M0 (done, result, data_A, data_B, start, clock, reset_b); initial #200 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork reset_b = 0; #2 reset_b = 1; #90 reset_b = 1; #92 reset_b = 1; join initial fork #20 start = 1; #30 start = 0; #70 start = 1; #110 start = 1; join initial fork data_A = 8'd50; data_B = 8'd20; #50 data_A = 8'd20; #50 data_B = 8'd50; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 257 #100 data_A = 8'd50; #100 data_B = 8'd50; join endmodule Name 0 40 80 120 clock reset_b state[1:0] 0 x 0 1 2 0 1 2 0 1 14 e2 1e 50 32 2 0 1 2 start Load_A_B Subtract carry borrow Convert data_A[7:0] RA[7:0] data_B[7:0] RB[7:0] done borrow result[7:0] 50 00 20 32 1e 20 00 0 14 50 50 00 32 0 50 32 30 20 226 30 50 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 8.8 258 RTL notation: S0: if (start = 1) AR ← input data, BR ← input data, go to S1. S1: if (AR [15]) = 1 (sign bit negative) then CR ← AR(shifted right, sign extension). else if (positive non-zero) then (Overflow ← BR([15] ⊕ [14]), CR ← BR(shifted left) else if (AR = 0) then (CR ← 0). data_AR data_BR AR_eq_0 AR_gt_0 16 AR_lt_0 16 Datapath Ld_AR_BR Controller Div_AR_x2_CR start Mul_BR_x2_CR done Clr_CR AR ... ... ... BR CR reset_b clock reset_b S0 done AR <= data_A BR<= data_B start 1 Ld_AR_BR S1 CR <= {AR[15], AR[15:1]} 1 AR < 0 Div_AR_x2_CR CR <= BR << 1 AR > 0 1 Mul_BR_x2_CR Note: Division by 2 of a negative number represented in 16-bit 2s complement format Note: Multiplication by 2 of a positive number represented in 16-bit 2s complement format CR <= 0 Clr_CR module Prob_8_8 (output done, input [15: 0] data_AR, data_BR, input start, clock, reset_b); Controller_P8_8 M0 ( Ld_AR_BR, Div_AR_x2_CR, Mul_BR_x2_CR, Clr_CR, done, start, AR_lt_0, AR_gt_0, AR_eq_0, clock, reset_b ); Datapath_P8_8 M1 ( Overflow, AR_lt_0, AR_gt_0, AR_eq_0, data_AR, data_BR, Ld_AR_BR, Div_AR_x2_CR, Mul_BR_x2_CR, Clr_CR, clock, reset_b ); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 259 module Controller_P8_8 ( output reg Ld_AR_BR, Div_AR_x2_CR, Mul_BR_x2_CR, Clr_CR, output done, input start, AR_lt_0, AR_gt_0, AR_eq_0, clock, reset_b ); parameter S0 = 1'b0, S1 = 1'b1; reg state, next_state; assign done = (state == S0); always @ (posedge clock, negedge reset_b) if (!reset_b) state <= S0; else state <= next_state; always @ (state, start, AR_lt_0, AR_gt_0, AR_eq_0) begin Ld_AR_BR = 0; Div_AR_x2_CR = 0; Mul_BR_x2_CR = 0; Clr_CR = 0; case (state) S0: if (start) begin Ld_AR_BR = 1; next_state = S1; end S1: begin next_state = S0; if (AR_lt_0) Div_AR_x2_CR = 1; else if (AR_gt_0) Mul_BR_x2_CR = 1; else if (AR_eq_0) Clr_CR = 1; end default: next_state = S0; endcase end endmodule module Datapath_P8_8 ( output reg Overflow, output AR_lt_0, AR_gt_0, AR_eq_0, input [15: 0] data_AR, data_BR, input Ld_AR_BR, Div_AR_x2_CR, Mul_BR_x2_CR, Clr_CR, clock, reset_b ); reg [15: 0] AR, BR, CR; assign AR_lt_0 = AR[15]; assign AR_gt_0 = (!AR[15]) && (| AR[14:0]); // Reduction-OR assign AR_eq_0 = (AR == 16'b0); always @ (posedge clock, negedge reset_b) if (!reset_b) begin AR <= 8'b0; BR <= 8'b0; CR <= 16'b0; end else begin if (Ld_AR_BR) begin AR <= data_AR; BR <= data_BR; end else if (Div_AR_x2_CR) CR <= {AR[15], AR[15:1]}; // For compiler without arithmetic right shift else if (Mul_BR_x2_CR) {Overflow, CR} <= (BR << 1); else if (Clr_CR) CR <= 16'b0; end endmodule // Test plan – Verify; // Power-up reset // If AR < 0 divide AR by 2 and transfer to CR // If AR > 0 multiply AR by 2 and transfer to CR // If AR = 0 clear CR // Reset on-the-fly Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 260 module t_Prob_P8_8; wire done; reg [15: 0] data_AR, data_BR; reg start, clock, reset_b; reg [15: 0] AR_mag, BR_mag, CR_mag; // To illustrate 2s complement math // Probes for displaying magnitude of numbers always @ (M0.M1.AR) // Hierarchical dereferencing if (M0.M1.AR[15]) AR_mag = ~M0.M1.AR+ 16'd1; else AR_mag = M0.M1.AR; always @ (M0.M1.BR ) if (M0.M1.BR[15]) BR_mag = ~M0.M1.BR+ 16'd1; else BR_mag = M0.M1.BR; always @ (M0.M1.CR) if (M0.M1.CR[15]) CR_mag = ~M0.M1.CR + 16'd1; else CR_mag = M0.M1.CR; Prob_8_8 M0 (done, data_AR, data_BR, start, clock, reset_b); initial #250 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork reset_b = 0; // Power-up reset #2 reset_b = 1; #50 reset_b = 0; // Reset on-the-fly #52 reset_b = 1; #90 reset_b = 1; #92 reset_b = 1; join initial fork #20 start = 1; #30 start = 0; #70 start = 1; #110 start = 1; join initial fork data_AR = 16'd50; data_BR = 16'd20; // AR > 0 // Result should be 40 #50 data_AR = 16'd20; #50 data_BR = 16'd50; // Result should be 100 #100 data_AR = 16'd50; #100 data_BR = 16'd50; #130 data_AR = 16'd0; // AR = 0, result should clear CR #160 data_AR = -16'd20; // AR < 0, Verilog stores 16-bit 2s complement #160 data_BR = 16'd50; // Result should have magnitude10 #190 data_AR = 16'd20; // AR < 0, Verilog stores 16-bit 2s complement #190 data_BR = 16'hffff; // Result should have overflow join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 261 Reset on-the-fly Name 0 60 120 180 240 reset_b clock start Divide by 2 and xfer to CR Multiply by 2 and xfer to CR AR_lt_0 AR_gt_0 AR_eq_0 state Ld_AR_BR Div_AR_x2_CR Mul_BR_x2_CR Clr_CR done data_AR[15:0] AR[15:0] AR[15:0] AR_mag[15:0] 50 BR[15:0] BR_mag[15:0] CR[15:0] CR[15:0] CR_mag[15:0] 50 0 65516 20 50 0 20 50 0 65516 20 0000 0032 0000 0014 0032 0000 ffec 0014 0 50 0 20 50 0 0 20 0 50 0000 0014 0000 0032 0 20 0 50 data_BR[15:0] BR[15:0] 20 0 20 0 50 40 0000 0 20 40 65535 65535 ffff 1 0 100 0 65526 65534 0000 0064 0 100 0000 fff6 fffe 0 10 2 Overflow Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 262 8.9 Design equations: DS_idle = S_2 + S_idle Start' DS_1 = S_idle Start + S_1 (A2 A3)' DS_2 = A2 A3 S_1 HDL description: module Prob_8_9 (output E, F, output [3: 0] A, output A2, A3, input Start, clock, reset_b); Controller_Prob_8_9 M0 (set_E, clr_E, set_F, clr_A_F, incr_A, Start, A2, A3, clock, reset_b); Datapath_Prob_8_9 M1 (E, F, A, A2, A3, set_E, clr_E, set_F, clr_A_F, incr_A, clock, reset_b); endmodule // Structural version of the controller (one-hot) // Note that the flip-flop for S_idle must have a set input and reset_b is wire to the set // Simulation results match Fig. 8-13 module Controller_Prob_8_9 ( output set_E, clr_E, set_F, clr_A_F, incr_A, input Start, A2, A3, clock, reset_b ); wire D_S_idle, D_S_1, D_S_2; wire q_S_idle, q_S_1, q_S_2; wire w0, w1, w2, w3; wire [2:0] state = {q_S_2, q_S_1, q_S_idle}; // Next-State Logic or (D_S_idle, q_S_2, w0); and (w0, q_S_idle, Start_b); not (Start_b, Start); or (D_S_1, w1, w2, w3); and (w1, q_S_idle, Start); and (w2, q_S_1, A2_b); not (A2_b, A2); and (w3, q_S_1, A2, A3_b); not (A3_b, A3); and (D_S_2, A2, A3, q_S_1); // input to D-type flip-flop for q_S_idle // input to D-type flip-flop for q_S_1 // input to D-type flip-flop for q_S_2 D_flop_S M0 (q_S_idle, D_S_idle, clock, reset_b); D_flop M1 (q_S_1, D_S_1, clock, reset_b); D_flop M2 (q_S_2, D_S_2, clock, reset_b); // Output Logic and (set_E, q_S_1, A2); and (clr_E, q_S_1, A2_b); buf (set_F, q_S_2); and (clr_A_F, q_S_idle, Start); buf (incr_A, q_S_1); endmodule module D_flop (output reg q, input data, clock, reset_b); always @ (posedge clock, negedge reset_b) if (!reset_b) q <= 1'b0; else q <= data; endmodule module D_flop_S (output reg q, input data, clock, set_b); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 263 always @ (posedge clock, negedge set_b) if (!set_b) q <= 1'b1; else q <= data; endmodule /* // RTL Version of the controller // Simulation results match Fig. 8-13 module Controller_Prob_8_9 ( output reg set_E, clr_E, set_F, clr_A_F, incr_A, input Start, A2, A3, clock, reset_b ); parameter S_idle = 3'b001, S_1 = 3'b010, S_2 = 3'b100; reg [2: 0] state, next_state; // One-hot always @ (posedge clock, negedge reset_b) if (!reset_b) state <= S_idle; else state <= next_state; always @ (state, Start, A2, A3) begin set_E = 1'b0; clr_E = 1'b0; set_F = 1'b0; clr_A_F = 1'b0; incr_A = 1'b0; case (state) S_idle: if (Start) begin next_state = S_1; clr_A_F = 1; end else next_state = S_idle; S_1: begin incr_A = 1; if (!A2) begin next_state = S_1; clr_E = 1; end else begin set_E = 1; if (A3) next_state = S_2; else next_state = S_1; end end S_2: begin next_state = S_idle; set_F = 1; end default: next_state = S_idle; endcase end endmodule */ module Datapath_Prob_8_9 ( output reg E, F, output reg [3: 0] A, output A2, A3, input set_E, clr_E, set_F, clr_A_F, incr_A, clock, reset_b ); assign A2 = A[2]; assign A3 = A[3]; always @ (posedge clock, negedge reset_b) begin if (!reset_b) begin E <= 0; F <= 0; A <= 0; end else begin if (set_E) E <= 1; if (clr_E) E <= 0; if (set_F) F <= 1; if (clr_A_F) begin A <= 0; F <= 0; end if (incr_A) A <= A + 1; end end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 264 // Test Plan - Verify: (1) Power-up reset, (2) match ASMD chart in Fig. 8-9 (d), // (3) recover from reset on-the-fly module t_Prob_8_9; wire E, F; wire [3: 0] A; wire A2, A3; reg Start, clock, reset_b; Prob_8_9 M0 (E, F, A, A2, A3, Start, clock, reset_b); initial #500 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin reset_b = 0; #2 reset_b = 1; end initial fork #20 Start = 1; #40 reset_b = 0; #62 reset_b = 1; join endmodule 8.10 reset_b s0 x 1 s1 1 y 0 s3 0 s2 x 1 y 0 x 1 0 1 y 1 module Prob_8_10 (input x, y, clock, reset_b); reg [ 1: 0] state, next_state; parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11; always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= s0; else state <= next_state; always @ (state, x, y) begin next_state = s0; case (state) s0: if (x == 0) next_state = s0; else next_state = s1; s1: if (y == 0) next_state = s2; else next_state = s3; s2: if (x == 0) next_state = s0; else if (y == 0) next_state = s2; else next_state = s3; s3: if (x == 0) next_state = s0; else if (y == 0) next_state = s2; else next_state = s3; endcase end endmodule module t_Prob_8_10 (); reg x, y, clock, reset_b; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 265 Prob_8_10 M0 (x, y, clock, reset_b); initial #150 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork reset_b = 0; #12 reset_b = 1; x = 0; y = 0; // Remain in s0 #10 y = 1; // Remain in s0 #20 x = 1; // Go to s1 to s3 #40 reset_b = 0; // Go to s0 #42 reset_b = 1; // Go to s2 to s3 #60 y = 0; // Go to s2 #80 y = 1; // Go to s3 #90 x = 0; // Go to s0 #100 x = 1; // Go to s1 #110 y = 0; // Go to s2 #130 x = 0; // Go to s0 join endmodule Name 0 50 100 150 clock reset_b x y state[1:0] 0 1 3 0 1 3 2 3 0 1 2 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 0 8.11 266 DA = Aʹ′B + Ax DB = Aʹ′Bʹ′x + Aʹ′By + xy state inputs 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 next state 0 0 0 0 AB 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 0 1 xy x 00 00 01 11 A 10 m0 m4 1 01 m1 m5 1 11 10 m3 m7 m2 m6 1 1 m12 m13 m15 m14 m8 m9 m11 m10 1 B 1 1 1 y DA = A'B + Ax AB xy x 00 00 01 11 A 10 01 11 10 m0 m1 m3 m4 m5 m7 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 1 1 m2 1 m6 B y DB = A'B' x + A'By + xy Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 8.12 267 For the 4-bit synchronous counter, modify the counter in Fig. 6.12 to add a signal, Clear, to clear the counter synchronously, as shown in the circuit diagram below. Count enable Clear J Q K QB J Q K QB J Q K QB J Q K QB A0 A1 A2 A3 To next stage CLK module Counter_4bit_Synch_Clr (output [3: 0] A, output next_stage, input Count_enable, Clear, CLK); wire A0, A1, A2, A3; assign A[3: 0] = {A3, A2, A1, A0}; JK_FF M0 (A0, J0, K0, CLK); JK_FF M1 (A1, J1, K1, CLK); JK_FF M2 (A2, J2, K2, CLK); JK_FF M3 (A3, J3, K3, CLK); not (Clear_b, Clear); and (J0, Count_enable, Clear_b); and (J1, J0, A0); and (J2, J1, A1); and (J3, J2, A2); or (K0, Clear, J0); or (K1, Clear, J1); or (K2, Clear, J2); or (K3, Clear, J3); and (next_stage, A3, J3); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 268 module JK_FF (output reg Q, input J, K, clock); always @ (posedge clock) case ({J,K}) 2'b00: Q <= Q; 2'b01: Q <= 0; 2'b10: Q <= 1; 2'b11: Q <= ~Q; endcase endmodule module t_Counter_4bit_Synch_Clr (); wire [3: 0] A; wire next_stage; reg Count_enable, Clear, clock; Counter_4bit_Synch_Clr M0 (A, next_stage, Count_enable, Clear, clock); initial #300 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork Clear = 1; Count_enable = 0; #12 Clear = 0; #20 Count_enable = 1; #180 Clear = 1; #190 Clear = 0; #230 Count_enable = 0; join endmodule Simulation results: synchronous clear. Name 0 50 100 150 200 250 clock Clear Count_enable J0 K0 A0 J1 K1 A1 J2 K2 A2 J3 K3 A3 A[3:0] x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 next_stage (b) module Counter_4bit_Asynch_Clr_b ( output [3: 0] A, output next_stage, input Count_enable, Clk, Clear_b ); wire A0, A1, A2, A3; assign A[3: 0] = {A3, A2, A1, A0}; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 4 269 wire J0, K0, J1, K1, J2, K2, J3, K3; assign K0 = J0; assign K1 = J1; assign K2 = J2; assign K3 = J3; JK_FF M0 (A0, J0, K0, Clk, Clear_b); JK_FF M1 (A1, J1, K1, Clk, Clear_b); JK_FF M2 (A2, J2, K2, Clk, Clear_b); JK_FF M3 (A3, J3, K3, Clk, Clear_b); and (J0, Count_enable); and (J1, J0, A0); and (J2, J1, A1); and (J3, J2, A2); and (next_stage, A3, J3); endmodule module JK_FF (output reg Q, input J, K, clock, Clear_b); always @ (posedge clock, negedge Clear_b) if (Clear_b == 1'b0) Q <= 0; else case ({J,K}) 2'b00: Q <= Q; 2'b01: Q <= 0; 2'b10: Q <= 1; 2'b11: Q <= ~Q; endcase endmodule module t_Counter_4bit_Asynch_Clr_b (); wire [3: 0] A; wire next_stage; reg Count_enable, Clk, Clear_b; Counter_4bit_Asynch_Clr_b M0 (A, next_stage, Count_enable, Clk, Clear_b); initial #200 $finish; initial begin Clk = 0; forever #5 Clk = ~Clk; end initial fork Count_enable = 0; Clear_b = 0; #30 Count_enable = 1; #50 Clear_b = 1; #90 Count_enable = 0; #110 Count_enable= 1; #150 Clear_b = 0; #170 Clear_b = 1; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 270 Count_enable J Q A0 Q A1 Q A2 Q A3 Clk K CLR Clear_b J K CLR J K CLR J K CLR next_stage Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 271 8.13 // Structural description of design example (Fig. 8-10, 8-12) module Design_Example_STR ( output [3:0] output input ); A, E, F, Start, clock, reset_b Controller_STR M0 (clr_A_F, set_E, clr_E, set_F, incr_A, Start, A[2], A[3], clock, reset_b ); Datapath_STR M1 (A, E, F, clr_A_F, set_E, clr_E, set_F, incr_A, clock); endmodule module Controller_STR ( output clr_A_F, set_E, clr_E, set_F, incr_A, input Start, A2, A3, clock, reset_b ); wire G0, G1; parameter S_idle = 2'b00, S_1 = 2'b01, S_2 = 2'b11; wire w1, w2, w3; not (G0_b, G0); not (G1_b, G1); buf (incr_A, w2); buf (set_F, G1); not (A2_b, A2); or (D_G0, w1, w2); and (w1, Start, G0_b); and (clr_A_F, G0_b, Start); and (w2, G0, G1_b); and (set_E, w2, A2); and (clr_E, w2, A2_b); and (D_G1, w3, w2); and (w3, A2, A3); D_flip_flop_AR M0 (G0, D_G0, clock, reset_b); D_flip_flop_AR M1 (G1, D_G1, clock, reset_b); endmodule // datapath unit module Datapath_STR ( output [3: 0] A, output E, F, input clr_A_F, set_E, clr_E, set_F, incr_A, clock ); JK_flip_flop_2 M0 (E, E_b, set_E, clr_E, clock); JK_flip_flop_2 M1 (F, F_b, set_F, clr_A_F, clock); Counter_4 M2 (A, incr_A, clr_A_F, clock); endmodule module Counter_4 (output reg [3: 0] A, input incr, clear, clock); always @ (posedge clock) if (clear) A <= 0; else if (incr) A <= A + 1; endmodule module D_flip_flop_AR (Q, D, CLK, RST); output Q; input D, CLK, RST; reg Q; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 272 always @ (posedge CLK, negedge RST) if (RST == 0) Q <= 1'b0; else Q <= D; endmodule module JK_flip_flop_2 (Q, Q_not, J, K, CLK); output Q, Q_not; input J, K, CLK; reg Q; assign Q_not = ~Q ; always @ (posedge CLK) case ({J, K}) 2'b00: Q <= Q; 2'b01: Q <= 1'b0; 2'b10: Q <= 1'b1; 2'b11: Q <= ~Q; endcase endmodule module t_Design_Example_STR; reg Start, clock, reset_b; wire [3: 0] A; wire E, F; wire [1:0] state_STR = {M0.M0.G1, M0.M0.G0}; Design_Example_STR M0 (A, E, F, Start, clock, reset_b); initial #500 $finish; initial begin reset_b = 0; Start = 0; clock = 0; #5 reset_b = 1; Start = 1; repeat (32) begin #5 clock = ~ clock; end end initial $monitor ("A = %b E = %b F = %b time = %0d", A, E, F, $time); endmodule The simulation results shown below match Fig. 8.13. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 273 Name 0 50 100 150 200 clock reset_b Start A2 A3 state_STR[1:0] 0 1 3 0 1 clr_A_F set_E clr_E set_F incr_A A[3:0] x 0 1 2 3 4 5 6 7 8 9 a b c d 0 E F 8.14 8.15 The state code 2'b10 is unused. If the machine enters an unused state, the controller is written with default assignment to next_state. The default assignment forces the state to S_idle, so the machine recovers from the condition. Modify the test bench to insert a reset event and extend the clock. // RTL description of design example (see Fig.8-11) module Design_Example_RTL (A, E, F, Start, clock, reset_b); // Specify ports of the top-level module of the design // See block diagram Fig. 8-10 output [3: 0] A; output E, F; input Start, clock, reset_b; // Instantiate controller and datapath units Controller_RTL M0 (set_E, clr_E, set_F, clr_A_F, incr_A, A[2], A[3], Start, clock, reset_b ); Datapath_RTL M1 (A, E, F, set_E, clr_E, set_F, clr_A_F, incr_A, clock); endmodule module Controller_RTL (set_E, clr_E, set_F, clr_A_F, incr_A, A2, A3, Start, clock, reset_b); output reg set_E, clr_E, set_F, clr_A_F, incr_A; input Start, A2, A3, clock, reset_b; reg [1:0] state, next_state; parameter S_idle = 2'b00, S_1 = 2'b01, S_2 = 2'b11; // State codes always @ (posedge clock or negedge reset_b) if (reset_b == 0) state <= S_idle; else state <= next_state; // State transitions (edge-sensitive) // Code next state logic directly from ASMD chart (Fig. 8-9d) always @ (state, Start, A2, A3 ) begin next_state = S_idle; case (state) // Next state logic (level-sensitive) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 274 S_idle: S_1: S_2: default: endcase end if (Start) next_state = S_1; else next_state = S_idle; if (A2 & A3) next_state = S_2; else next_state = S_1; next_state = S_idle; next_state = S_idle; // Code output logic directly from ASMD chart (Fig. 8-9d) always @ (state, Start, A2) begin set_E = 0; // default assignments; assign by exception clr_E = 0; set_F = 0; clr_A_F = 0; incr_A = 0; case (state) S_idle: if (Start) clr_A_F = 1; S_1: begin incr_A = 1; if (A2) set_E = 1; else clr_E = 1; end S_2: set_F = 1; endcase end endmodule module Datapath_RTL (A, E, F, set_E, clr_E, set_F, clr_A_F, incr_A, clock); output reg [3: 0] A; // register for counter output reg E, F; // flags input set_E, clr_E, set_F, clr_A_F, incr_A, clock; // Code register transfer operations directly from ASMD chart (Fig. 8-9d) always @ (posedge clock) begin if (set_E) E <= 1; if (clr_E) E <= 0; if (set_F) F <= 1; if (clr_A_F) begin A <= 0; F <= 0; end if (incr_A) A <= A + 1; end endmodule module t_Design_Example_RTL; reg Start, clock, reset_b; wire [3: 0] A; wire E, F; // Instantiate design example Design_Example_RTL M0 (A, E, F, Start, clock, reset_b); // Describe stimulus waveforms initial #500 $finish; // Stopwatch initial fork #25 reset_b = 0; // Test for recovery from reset on-the-fly. #27 reset_b = 1; join initial begin reset_b = 0; Start = 0; clock = 0; #5 reset_b = 1; Start = 1; //repeat (32) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 275 repeat (38) // Modify for test of reset_b on-the-fly begin #5 clock = ~ clock; // Clock generator end end initial $monitor ("A = %b E = %b F = %b time = %0d", A, E, F, $time); endmodule Name 0 40 80 120 160 200 Default clock reset_b Start A2 A3 state[1:0] 0 1 0 1 3 0 1 clr_A_F set_E clr_E set_F incr_A A[3:0] x 0 1 0 1 2 3 4 5 6 7 8 9 a b c d 0 1 E F 8.16 RTL notation: s0: (initial state) If start = 0 go back to state s0, If (start = 1) then BR ← multiplicand, AR ← multiplier, PR ← 0, go to s1. s1: (check AR for Zero) Zero = 1 if AR = 0, if (Zero = 1) then go back to s0 (done) If (Zero = 0) then go to s1, PR ← PR + BR, AR ← AR – 1. The internal architecture of the datapath consists of a double-width register to hold the product (PR), a register to hold the multiplier (AR), a register to hold the multiplicand (BR), a double-width parallel adder, and single-width parallel adder. The single-width adder is used to implement the operation of decrementing the multiplier unit. Adding a word consisting entirely of 1s to the multiplier accomplishes the 2's complement subtraction of 1 from the multiplier. Figure 8.16 (a) below shows the ASMD chart, block diagram, and controller of the circuit. Figure 8.16 (b) shows the internal architecture of the datapath. Figure 8.16 (c) shows the results of simulating the circuit. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 276 reset_b s0 done data_AR data_BR AR <= data_A BR <= data_B PR <= 0 start 16 zero 1 Ld_regs PR <= PR + BR AR <= AR -1 Controller Add_decr Datapath AR ... BR ... PR ... Ld_regs s1 Zero 1 16 Add_decr start done reset_b clock 16 PR Note: Form Zero as the output of an OR gate whose inputs are the bits of the register AR. Add_decr Controller s0 = s1' Zero done D Start clock reset_b Ld_regs (a) ASMD chart, block diagram, and controller Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 277 data_BR 16 1 Ld_regs mux 0 16 ... All 0's BR 1 Add_decr 32 0 + 16 data_AR 16 32 mux 16 Note: all registers have active-low asynchronous reset 1 Ld_regs mux 32 0 16 ... ... PR ... ... 32 AR 16 16 0 mux Ld_regs 1 + 32 1 mux 0 Add_decr 0 16 A// 1s (b) Datapath Name 0 40 80 120 160 200 reset_b clock start Ld_regs Add_decr zero state data_AR[7:0] 5 data_BR[7:0] 20 AR[7:0] BR[7:0] 0 3 4 9 5 4 3 2 0 1 0 4 3 2 20 1 0 4 36 0 9 done PR[15:0] 0 20 40 60 80 100 0 9 18 27 (c) Simulation results Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 278 module Prob_8_16_STR ( output [15: 0] PR, output done, input [7: 0] data_AR, data_BR, input start, clock, reset_b ); Controller_P8_16 M0 (done, Ld_regs, Add_decr, start, zero, clock, reset_b); Datapath_P8_16 M1 (PR, zero, data_AR, data_BR, Ld_regs, Add_decr, clock, reset_b); endmodule module Controller_P8_16 (output done, output reg Ld_regs, Add_decr, input start, zero, clock, reset_b); parameter s0 = 1'b0, s1 = 1'b1; reg state, next_state; assign done = (state == s0); always @ (posedge clock, negedge reset_b) if (!reset_b) state <= s0; else state <= next_state; always @ (state, start, zero) begin Ld_regs = 0; Add_decr = 0; case (state) s0: if (start) begin Ld_regs = 1; next_state = s1; end s1: if (zero) next_state = s0; else begin next_state = s1; Add_decr = 1; end default: next_state = s0; endcase end endmodule module Register_32 (output [31: 0] data_out, input [31: 0] data_in, input clock, reset_b); Register_8 M3 (data_out [31: 24] , data_in [31: 24], clock, reset_b); Register_8 M2 (data_out [23: 16] , data_in [23: 16], clock, reset_b); Register_8 M1 (data_out [15: 8] , data_in [15: 8], clock, reset_b); Register_8 M0 (data_out [7: 0] , data_in [7: 0], clock, reset_b); endmodule module Register_16 (output [15: 0] data_out, input [15: 0] data_in, input clock, reset_b); Register_8 M1 (data_out [15: 8] , data_in [15: 8], clock, reset_b); Register_8 M0 (data_out [7: 0] , data_in [7: 0], clock, reset_b); endmodule module Register_8 (output [7: 0] data_out, input [7: 0] data_in, input clock, reset_b); D_flop M7 (data_out[7] data_in[7], clock, reset_b); D_flop M6 (data_out[6] data_in[6], clock, reset_b); D_flop M5 (data_out[5] data_in[5], clock, reset_b); D_flop M4 (data_out[4] data_in[4], clock, reset_b); D_flop M3 (data_out[3] data_in[3], clock, reset_b); D_flop M2 (data_out[2] data_in[2], clock, reset_b); D_flop M1 (data_out[1] data_in[1], clock, reset_b); D_flop M0 (data_out[0] data_in[0], clock, reset_b); endmodule module Adder_32 (output c_out, output [31: 0] sum, input [31: 0] a, b); assign {c_out, sum} = a + b; endmodule module Adder_16 (output c_out, output [15: 0] sum, input [15: 0] a, b); assign {c_out, sum} = a + b; endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 279 module D_flop (output q, input data, clock, reset_b); always @ (posedge clock, negedge reset_b) if (!reset_b) q <= 0; else q <= data; endmodule module Datapath_P8_16 ( output reg [15: 0] PR, output zero, input [7: 0] data_AR, data_BR, input Ld_regs, Add_decr, clock, reset_b ); reg [7: 0] AR, BR; assign zero = ~( | AR); always @ (posedge clock, negedge reset_b) if (!reset_b) begin AR <= 8'b0; BR <= 8'b0; PR <= 16'b0; end else begin if (Ld_regs) begin AR <= data_AR; BR <= data_BR; PR <= 0; end else if (Add_decr) begin PR <= PR + BR; AR <= AR -1; end end endmodule // Test plan – Verify; // Power-up reset // Data is loaded correctly // Control signals assert correctly // Status signals assert correctly // start is ignored while multiplying // Multiplication is correct // Recovery from reset on-the-fly module t_Prob_P8_16; wire done; wire [15: 0] PR; reg [7: 0] data_AR, data_BR; reg start, clock, reset_b; Prob_8_16_STR M0 (PR, done, data_AR, data_BR, start, clock, reset_b); initial #500 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork reset_b = 0; #12 reset_b = 1; #40 reset_b = 0; #42 reset_b = 1; #90 reset_b = 1; #92 reset_b = 1; join initial fork #20 start = 1; #30 start = 0; #40 start = 1; #50 start = 0; #120 start = 1; #120 start = 0; join Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 280 initial fork data_AR = 8'd5; data_BR = 8'd20; // AR > 0 #80 data_AR = 8'd3; #80 data_BR = 8'd9; #100 data_AR = 8'd4; #100 data_BR = 8'd9; join endmodule 8.17 8.18 (2n – 1) (2n – 1) < (22n – 1) for n ≥ 1 (a) The maximum product size is 32 bits available in registers A and Q. (b) P counter must have 5 bits to load 16 (binary 10000) initially. (c) Z (zero) detection is generated with a 5-input NOR gate. 8.19 Multiplicand B = 110112 = 2710 Multiplier Q = 101112 = 2310 Product: CAQ = 62110 Multiplier in Q Q0 = 1; add B First partial product Shift right CAQ Q0 = 1; add B Second partial product Shift right CAQ Q0 = 1; add B Third partial product Shift right CAQ Shift right CAQ Fourth partial product Q0 = 1; add B Fifth partial product Shift right CAQ Final product in AQ: AQ = 10011_01101 = 62110 8.20 C 0 0 0 1 0 1 0 0 0 1 0 A 00000 11011 11011 01101 11011 01000 10100 11011 01111 10111 Q 10111 P 101 10111 11011 100 11011 01101 011 01101 10110 010 01011 01011 11011 00110 10011 11011 11011 11011 01101 001 000 S_idle = 1t ns The loop between S_add and S_shift takes 2nt ns) Total time to multiply: (2n + 1)t 8.21 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 281 State codes: S_idle S_add S_shift1 unused 0 0 1 1 Zero' 0 Mux_1 G1 0 0 0 0 G0 0 1 0 G1 D Start 2 3 s1 Load_regs C s0 Q[0] 0 Add_regs 1 2 x 4 Decoder 2 Shift_regs 3 Start 0 0 1 0 2 0 3 s1 s0 Mux_2 G0 D C clock reset_b 8.22 Note that the machine described by Fig. P8.22 requires four states, but the machine described byFig. 8.15 (b) requires only three. Also, observe that the sample simulation results show a case where the carry bit regsiter, C, is needed to support the addition operation. The datapath is 8 bits wide. module Prob_8_22 # (parameter m_size = 9) ( output [2*m_size -1: 0] Product, output Ready, input [m_size -1: 0] Multiplicand, Multiplier, input Start, clock, reset_b ); wire [m_size -1: 0] A, Q; assign Product = {A, Q}; wire Q0, Zero, Load_regs, Decr_P, Add_regs, Shift_regs; Datapath_Unit M0 (A, Q, Q0, Zero, Multiplicand, Multiplier, Load_regs, Decr_P, Add_regs, Shift_regs, clock, reset_b); Control_Unit M1 (Ready, Decr_P, Load_regs, Add_regs, Shift_regs, Start, Q0, Zero, clock, reset_b); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 282 module Datapath_Unit # (parameter m_size = 9, BC_size = 4) ( output reg [m_size -1: 0] A, Q, output Q0, Zero, input [m_size -1: 0] Multiplicand, Multiplier, input Load_regs, Decr_P, Add_regs, Shift_regs, clock, reset_b ); reg C; reg [BC_size -1: 0] P; reg [m_size -1: 0] B; assign Q0 = Q[0]; assign Zero = (P == 0); always @ (posedge clock, negedge reset_b) if (reset_b == 0) begin B <= 0;C <= 0; A <= 0; Q <= 0; P <= m_size; end else begin if (Load_regs) begin A <= 0; C <= 0; Q <= Multiplier; B <= Multiplicand; P <= m_size; end if (Decr_P) P <= P -1; if (Add_regs) {C, A} <= A + B; if (Shift_regs) {C, A, Q} <= {C, A, Q} >> 1; end endmodule module Control_Unit ( output Ready, Decr_P, output reg Load_regs, Add_regs, Shift_regs, input Start, Q0, Zero, clock, reset_b ); reg [ 1: 0] state, next_state; parameter S_idle = 2'b00, S_loaded = 2'b01, S_sum = 2'b10, S_shifted = 2'b11; assign Ready = (state == S_idle); assign Decr_P = (state == S_loaded); always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= S_idle; else state <= next_state; always @ (state, Start, Q0, Zero) begin next_state = S_idle; Load_regs = 0; Add_regs = 0; Shift_regs = 0; case (state) S_idle: if (Start == 0) next_state = S_idle; else begin next_state = S_loaded; Load_regs = 1; end S_loaded: if (Q0) begin next_state = S_sum; Add_regs = 1; end else begin next_state = S_shifted; Shift_regs = 1; end S_sum: begin next_state = S_shifted; Shift_regs = 1; end S_shifted: if (Zero) next_state = S_idle; else next_state = S_loaded; endcase end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 283 module t_Prob_8_22 (); parameter m_size = 9; // Width of datapath wire [2 * m_size - 1: 0] Product; wire Ready; reg [m_size - 1: 0] Multiplicand, Multiplier; reg Start, clock, reset_b; integer Exp_Value; reg Error; Prob_8_22 M0 (Product, Ready, Multiplicand, Multiplier, Start, clock, reset_b); initial #140000 $finish; initial begin clock = 0; #5 forever #5 clock = ~clock; end initial fork reset_b = 1; #2 reset_b = 0; #3 reset_b = 1; join initial begin #5 Start = 1; end always @ (posedge Ready) begin Exp_Value = Multiplier * Multiplicand; //Exp_Value = Multiplier * Multiplicand +1; end always @ (negedge Ready) begin Error = (Exp_Value ^ Product) ; end // Inject error to confirm detection initial begin #5 Multiplicand = 0; Multiplier = 0; repeat (64) #10 begin Multiplier = Multiplier + 1; repeat (64) @ (posedge M0.Ready) #5 Multiplicand = Multiplicand + 1; end end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 284 Name 76811 76861 76911 76961 77011 clock reset_b Ready Start Load_regs Add_regs Shift_regs Decr_P Q0 Zero state[1:0] 0 1 P[3:0] 0 9 3 1 8 2 3 1 7 2 3 1 6 3 1 3 5 1 4 3 1 3 3 1 2 3 1 1 3 0 0 1 3 8 177 B[8:0] 1 9 178 C A[8:0] 000 0bb Q[8:0] 003 Product[17:0] 3 101 119 08c 046 023 011 008 004 080 140 0a0 050 128 194 0ca 72000 36000 18000 9000 4500 2250 96001 003 3 375 Multiplicand[8:0] 376 6 Multiplier[8:0] Product[17:0] 000 3 96001 72000 36000 18000 9000 4500 2250 3 Ready Exp_Value 2244 2250 Error 8.23 As shown in Fig. P8.23 the machine asserts Load_regs in state S_load. This will cause the machine to operate incorrectly. Once Load_regs is removed from S_load the machine operates correctly. The state S_load is a wasted state. Its removal leads to the same machine as dhown in Fig. P8.15b. module Prob_8_23 # (parameter m_size = 9) ( output [2*m_size -1: 0] Product, output Ready, input [m_size -1: 0] Multiplicand, Multiplier, input Start, clock, reset_b ); wire [m_size -1: 0] A, Q; assign Product = {A, Q}; wire Q0, Zero, Load_regs, Decr_P, Add_regs, Shift_regs; Datapath_Unit M0 (A, Q, Q0, Zero, Multiplicand, Multiplier, Load_regs, Decr_P, Add_regs, Shift_regs, clock, reset_b); Control_Unit M1 (Ready, Decr_P, Shift_regs, Add_regs, Load_regs, Start, Q0, Zero, clock, reset_b); endmodule module Datapath_Unit # (parameter m_size = 9, BC_size = 4) ( output reg [m_size -1: 0] A, Q, output Q0, Zero, input [m_size -1: 0] Multiplicand, Multiplier, input Load_regs, Decr_P, Add_regs, Shift_regs, clock, reset_b ); reg C; reg [BC_size -1: 0] P; reg [m_size -1: 0] B; assign Q0 = Q[0]; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 285 assign Zero = (P == 0); always @ (posedge clock, negedge reset_b) if (reset_b == 0) begin A <= 0; C <= 0; Q <= 0; B <= 0; P <= m_size; end else begin if (Load_regs) begin A <= 0; C <= 0; Q <= Multiplier; B <= Multiplicand; P <= m_size; end if (Decr_P) P <= P -1; if (Add_regs) {C, A} <= A + B; if (Shift_regs) {C, A, Q} <= {C, A, Q} >> 1; end endmodule module Control_Unit ( output Ready, Decr_P, Shift_regs, output reg Add_regs, Load_regs, input Start, Q0, Zero, clock, reset_b ); reg [ 1: 0] state, next_state; parameter S_idle = 2'b00, S_load = 2'b01, S_decr = 2'b10, S_shift = 2'b11; assign Ready = (state == S_idle); assign Shift_regs = (state == S_shift); assign Decr_P = (state == S_decr); always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= S_idle; else state <= next_state; always @ (state, Start, Q0, Zero) begin next_state = S_idle; Load_regs = 0; Add_regs = 0; case (state) S_idle: if (Start == 0) next_state = S_idle; else begin next_state = S_load; Load_regs = 1; end S_load: begin next_state = S_decr; end S_decr: begin next_state = S_shift; if (Q0) Add_regs = 1; end S_shift: if (Zero) next_state = S_idle; else next_state = S_load; endcase end endmodule module t_Prob_8_23 (); parameter m_size = 9; // Width of datapath wire [2 * m_size - 1: 0] Product; wire Ready; reg [m_size - 1: 0] Multiplicand, Multiplier; reg Start, clock, reset_b; integer Exp_Value; reg Error; Prob_8_23 M0 (Product, Ready, Multiplicand, Multiplier, Start, clock, reset_b); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 286 initial #140000 $finish; initial begin clock = 0; #5 forever #5 clock = ~clock; end initial fork reset_b = 1; #2 reset_b = 0; #3 reset_b = 1; join initial begin #5 Start = 1; end always @ (posedge Ready) begin Exp_Value = Multiplier * Multiplicand; //Exp_Value = Multiplier * Multiplicand +1; end always @ (negedge Ready) begin Error = (Exp_Value ^ Product) ; end // Inject error to confirm detection initial begin #5 Multiplicand = 0; Multiplier = 0; repeat (64) #10 begin Multiplier = Multiplier + 1; repeat (64) @ (posedge M0.Ready) #5 Multiplicand = Multiplicand + 1; end end endmodule Name 21403 21433 21463 21493 21523 21553 clock reset_b Ready Start Load_regs Add_regs Shift_regs Decr_P Q0 Zero state[1:0] 3 1 2 5 P[3:0] 3 1 2 4 3 1 2 3 3 1 2 2 3 1 2 3 1 0 1 0 9 04c B[8:0] 04d C A[8:0] 013 Q[8:0] 000 Product[17:0] 002 001 100 180 0c0 060 4864 009 2432 004 1216 000 130 304 098 002 152 2 76 Multiplicand[8:0] 77 2 Multiplier[8:0] Product[17:0] 608 4864 2432 1216 608 304 152 2 Ready Exp_Value 150 Error Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 152 287 8.24 module Prob_8_24 # (parameter dp_width = 5) ( output [2*dp_width - 1: 0] Product, output Ready, input [dp_width - 1: 0] Multiplicand, Multiplier, input Start, clock, reset_b ); wire Load_regs, Decr_P, Add_regs, Shift_regs, Zero, Q0; Controller M0 ( Ready, Load_regs, Decr_P, Add_regs, Shift_regs, Start, Zero, Q0, clock, reset_b ); Datapath M1(Product, Q0, Zero,Multiplicand, Multiplier, Start, Load_regs, Decr_P, Add_regs, Shift_regs, clock, reset_b); endmodule module Controller ( output Ready, output reg Load_regs, Decr_P, Add_regs, Shift_regs, input Start, Zero, Q0, clock, reset_b ); parameter reg [2: 0] assign S_idle = 3'b001, // one-hot code S_add = 3'b010, S_shift = 3'b100; state, next_state; // sized for one-hot Ready = (state == S_idle); always @ (posedge clock, negedge reset_b) if (~reset_b) state <= S_idle; else state <= next_state; always @ (state, Start, Q0, Zero) begin next_state = S_idle; Load_regs = 0; Decr_P = 0; Add_regs = 0; Shift_regs = 0; case (state) S_idle: if (Start) begin next_state = S_add; Load_regs = 1; end S_add: begin next_state = S_shift; Decr_P = 1; if (Q0) Add_regs = 1; end S_shift: begin Shift_regs = 1; if (Zero) next_state = S_idle; else next_state = S_add; end default: next_state = S_idle; endcase end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 288 module Datapath #(parameter dp_width = 5, BC_size = 3) ( output [2*dp_width - 1: 0] Product, output Q0, output Zero, input [dp_width - 1: 0] Multiplicand, Multiplier, input Start, Load_regs, Decr_P, Add_regs, Shift_regs, clock, reset_b ); // Default configuration: 5-bit datapath reg [dp_width - 1: 0] A, B, Q; // Sized for datapath reg C; reg [BC_size - 1: 0] P; // Bit counter assign Q0 = Q[0]; assign Zero = (P == 0); // Counter is zero assign Product = {C, A, Q}; always @ (posedge clock, negedge reset_b) if (reset_b == 0) begin // Added to this solution, but P <= dp_width; // not really necessary since Load_regs B <= 0; // initializes the datapath C <= 0; A <= 0; Q <= 0; end else begin if (Load_regs) begin P <= dp_width; A <= 0; C <= 0; B <= Multiplicand; Q <= Multiplier; end if (Add_regs) {C, A} <= A + B; if (Shift_regs) {C, A, Q} <= {C, A, Q} >> 1; if (Decr_P) P <= P -1; end endmodule module t_Prob_8_24; parameter wire [2 * dp_width - 1: 0] wire reg [dp_width - 1: 0] reg integer reg dp_width = 5; // Width of datapath Product; Ready; Multiplicand, Multiplier; Start, clock, reset_b; Exp_Value; Error; Prob_8_24 M0(Product, Ready, Multiplicand, Multiplier, Start, clock, reset_b); initial #115000 $finish; initial begin clock = 0; #5 forever #5 clock = ~clock; end initial fork reset_b = 1; #2 reset_b = 0; #3 reset_b = 1; join always @ (negedge Start) begin Exp_Value = Multiplier * Multiplicand; //Exp_Value = Multiplier * Multiplicand +1; // Inject error to confirm detection end always @ (posedge Ready) begin # 1 Error <= (Exp_Value ^ Product) ; end initial begin Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 289 #5 Multiplicand = 0; Multiplier = 0; repeat (32) #10 begin Start = 1; #10 Start = 0; repeat (32) begin Start = 1; #10 Start = 0; #100 Multiplicand = Multiplicand + 1; end Multiplier = Multiplier + 1; end end endmodule Name 45340 45380 45420 45460 45500 clock reset_b Start Load_regs Add_regs Shift_regs Decr_P Q0 Zero P[2:0] 1 0 5 4 3 2 19 B[4:0] 1 0 5 1a 4 1b C A[4:0] 18 Q[4:0] 18 Multiplicand[4:0] 9 0 0c 26 06 25 7 01 19 9 10 18 26 0 0c 27 12 Multiplier[4:0] Product[9:0] 13 03 600 300 12 6 3 835 417 225 624 312 12 Ready Exp_Value 300 312 Error Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 324 290 8.25 (a) Ready Multiplicand reset Datapath Empty Load_regs A Shift_regs Controller Start Multiplier Add_regs Decr_P B S_idle Ready Q Start 1 P C A <= 0 C <= 0 B <= Multiplicand Q <= Multiplier P <= m_size Load_regs reset clock Product Zero Q[0] Empty 1 Register B (Multiplicand) 1 1 0 7 1 0 1 1 Register P (Counter) 1 1 0 0 0 Q[0] Clr_P {C, A} <= A + B 1 0 8 P <= P-1 S_add Decr_P Add_regs + 16 15 0 9 C 8 0 0 0 0 0 Register A (Sum) 0 8 7 0 0 0 0 0 1 0 1 1 S_shift Shift_regs 1 Register Q (Multiplier) {C, A, Q} <= {C, A, Q} >> 1 1 Empty Zero 1 (b) // The multiplier of Fig. 8.15 is modified to detect whether the multiplier or multiplicand are initially zero, // and to detect whether the multiplier becomes zero before the entire multiplier has been applied // to the multiplicand. Signal empty is generated by the datapath unit and used by the // controller. Note that the bits of the product must be selected according to the stage at which // termination occurs. The test for the condition of an empty multiplier is hardwired here for // dp_width = 5 because the range bounds of a vector must be defined by integer constants. // This prevents development of a fully parameterized model. // Note: the test bench has been modified. module Prob_8_25 #(parameter dp_width = 5) ( output [2*dp_width - 1: 0] Product, output Ready, input [dp_width - 1: 0] Multiplicand, Multiplier, input Start, clock, reset_b ); wire Load_regs, Decr_P, Add_regs, Shift_regs, Empty, Zero, Q0; Controller M0 ( Ready, Load_regs, Decr_P, Add_regs, Shift_regs, Start, Empty, Zero, Q0, clock, reset_b ); Datapath M1(Product, Q0, Empty, Zero,Multiplicand, Multiplier, Start, Load_regs, Decr_P, Add_regs, Shift_regs, clock, reset_b); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 291 module Controller ( output Ready, output reg Load_regs, Decr_P, Add_regs, Shift_regs, input Start, Empty, Zero, Q0, clock, reset_b ); parameter parameter reg [2: 0] assign BC_size = 3; // Size of bit counter S_idle = 3'b001, // one-hot code S_add = 3'b010, S_shift = 3'b100; state, next_state; // sized for one-hot Ready = (state == S_idle); always @ (posedge clock, negedge reset_b) if (~reset_b) state <= S_idle; else state <= next_state; always @ (state, Start, Q0, Empty, Zero) begin next_state = S_idle; Load_regs = 0; Decr_P = 0; Add_regs = 0; Shift_regs = 0; case (state) S_idle: if (Start) begin next_state = S_add; Load_regs = 1; end S_add: begin next_state = S_shift; Decr_P = 1; if (Q0) Add_regs = 1; end S_shift: begin Shift_regs = 1; if (Zero) next_state = S_idle; else if (Empty) next_state = S_idle; else next_state = S_add; end default: next_state = S_idle; endcase end endmodule module Datapath #(parameter dp_width = 5, BC_size = 3) ( output reg [2*dp_width - 1: 0] Product, output Q0, output Empty, output Zero, input [dp_width - 1: 0] Multiplicand, Multiplier, input Start, Load_regs, Decr_P, Add_regs, Shift_regs, clock, reset_b ); // Default configuration: 5-bit datapath parameter S_idle = 3'b001, // one-hot code S_add = 3'b010, S_shift = 3'b100; reg [dp_width - 1: 0] A, B, Q; // Sized for datapath reg C; reg [BC_size - 1: 0] P; // Bit counter wire [2*dp_width -1: 0] Internal_Product = {C, A, Q}; assign assign Q0 = Q[0]; Zero = (P == 0); // Bit counter is zero always @ (posedge clock, negedge reset_b) if (reset_b == 0) begin // Added to this solution, but P <= dp_width; // not really necessary since Load_regs B <= 0; // initializes the datapath C <= 0; A <= 0; Q <= 0; end else begin Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 292 if (Load_regs) begin P <= dp_width; A <= 0; C <= 0; B <= Multiplicand; Q <= Multiplier; end if (Add_regs) {C, A} <= A + B; if (Shift_regs) {C, A, Q} <= {C, A, Q} >> 1; if (Decr_P) P <= P -1; end // Status signals reg Empty_multiplier; wire Empty_multiplicand = (Multiplicand == 0); assign Empty = Empty_multiplicand || Empty_multiplier; always @ (P, Internal_Product) begin // Note: hardwired for dp_width 5 Product = 0; case (P) // Examine multiplier bits 0: Product = Internal_Product; 1: Product = Internal_Product [2*dp_width -1: 1]; 2: Product = Internal_Product [2*dp_width -1: 2]; 3: Product = Internal_Product [2*dp_width -1: 3]; 4: Product = Internal_Product [2*dp_width -1: 4]; 5: Product = 0; endcase end always @ (P, Q) begin // Note: hardwired for dp_width 5 Empty_multiplier = 0; case (P) 0: Empty_multiplier = 1; 1: if (Q[1] == 0) Empty_multiplier = 1; 2: if (Q[2: 1] == 0) Empty_multiplier = 1; 3: if (Q[3: 1] == 0) Empty_multiplier = 1; 4: if (Q[4: 1] == 0) Empty_multiplier = 1; 5: if (Q[5: 1] == 0) Empty_multiplier = 1; default: Empty_multiplier = 1'bx; endcase end endmodule module t_Prob_8_25; parameter dp_width = 5; // Width of datapath wire [2 * dp_width - 1: 0] Product; wire Ready; reg [dp_width - 1: 0] Multiplicand, Multiplier; reg Start, clock, reset_b; integer Exp_Value; reg Error; Prob_8_25 M0(Product, Ready, Multiplicand, Multiplier, Start, clock, reset_b); initial #115000 $finish; initial begin clock = 0; #5 forever #5 clock = ~clock; end initial fork reset_b = 1; #2 reset_b = 0; #3 reset_b = 1; join always @ (negedge Start) begin Exp_Value = Multiplier * Multiplicand; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 293 //Exp_Value = Multiplier * Multiplicand +1; end always @ (posedge Ready) begin # 1 Error <= (Exp_Value ^ Product) ; end // Inject error to confirm detection initial begin #5 Multiplicand = 0; Multiplier = 0; repeat (32) #10 begin Start = 1; #10 Start = 0; repeat (32) begin Start = 1; #10 Start = 0; #100 Multiplicand = Multiplicand + 1; end Multiplier = Multiplier + 1; end end endmodule (c) Test plan: Exhaustively test all combinations of multiplier and multiplicand, using automatic error checking. Verify that early termination is implemented. Sample of simulation results is shown below. Name 6902 6992 7082 7172 reset_b clock Start state[2:0] 1 2 4 1 2 4 1 2 4 2 Early termination Empty_multiplicand Empty_multiplier Empty Clr_CAQ Load_regs Decr_P Add_regs Shift_regs Q0 P[4:0] 4 5 4 5 4 5 4 Zero B[4:0] 30 A[4:0] 15 31 0 1 15 0 C Q[4:0] Multiplicand[4:0] 0 16 30 31 2 1 2 0 1 1 1 Multiplier[4:0] Product[9:0] 1 2 30 31 0 Ready Exp_Value 30 31 0 Error 8.26 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 2 294 reset S_idle /Ready A <= 0 C <= 0 B <= Multiplicand Q <= Multiplier P <= m_size Start 1 Load_regs P <= P-1 S_add_shift / Decr_P {C, A, Q} <= {A + B, Q} >> 1 Q[0] 1 Add_Shift Zero 1 Zero 1 module Prob_8_26 (Product, Ready, Multiplicand, Multiplier, Start, clock, reset_b); // Default configuration: 5-bit datapath parameter dp_width = 5; // Set to width of datapath output [2*dp_width - 1: 0] Product; output Ready; input [dp_width - 1: 0] Multiplicand, Multiplier; input Start, clock, reset_b; parameter BC_size = 3; // Size of bit counter parameter S_idle = 2'b01, // one-hot code S_add_shift = 2'b10; reg [2: 0] state, next_state; reg [dp_width - 1: 0] A, B, Q; // Sized for datapath reg C; reg [BC_size -1: 0] P; reg Load_regs, Decr_P, Add_shift, Shift; assign Product = {C, A, Q}; wire Zero = (P == 0); // counter is zero wire Ready = (state == S_idle); // controller status // control unit always @ (posedge clock, negedge reset_b) if (~reset_b) state <= S_idle; else state <= next_state; always @ (state, Start, Q[0], Zero) begin next_state = S_idle; Load_regs = 0; Decr_P = 0; Add_shift = 0; Shift = 0; case (state) S_idle: begin if (Start) next_state = S_add_shift; Load_regs = 1; end S_add_shift: begin Decr_P = 1; if (Zero) next_state = S_idle; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 295 default: endcase end else begin next_state = S_add_shift; if (Q[0]) Add_shift = 1; else Shift = 1; end end next_state = S_idle; // datapath unit always @ (posedge clock) begin if (Load_regs) begin P <= dp_width; A <= 0; C <= 0; B <= Multiplicand; Q <= Multiplier; end if (Decr_P) P <= P -1; if (Add_shift) {C, A, Q} <= {C, A+B, Q} >> 1; if (Shift) {C, A, Q} <= {C, A, Q} >> 1; end endmodule module t_Prob_8_26; parameter dp_width = 5; // Width of datapath wire [2 * dp_width - 1: 0] Product; wire Ready; reg [dp_width - 1: 0] Multiplicand, Multiplier; reg Start, clock, reset_b; integer Exp_Value; wire Error; Prob_8_26 M0 (Product, Ready, Multiplicand, Multiplier, Start, clock, reset_b); initial #70000 $finish; initial begin clock = 0; #5 forever #5 clock = ~clock; end initial fork reset_b = 1; #2 reset_b = 0; #3 reset_b = 1; join initial begin #5 Start = 1; end always @ (posedge Ready) begin Exp_Value = Multiplier * Multiplicand; end assign Error = Ready & (Exp_Value ^ Product); initial begin #5 Multiplicand = 0; Multiplier = 0; repeat (32) #10 begin Multiplier = Multiplier + 1; repeat (32) @ (posedge M0.Ready) #5 Multiplicand = Multiplicand + 1; end end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 296 Sample of simulation results. Name 23982 24042 24102 24162 clock reset_b Start Load_regs Shift Add_shift Decr_P P[2:0] 2 1 0 7 5 4 3 2 22 B[4:0] 1 0 7 5 4 3 2 23 1 0 7 5 4 24 25 C A[4:0] 0 11 5 Q[4:0] 9 4 18 Multiplicand[4:0] 22 11 1 11 21 0 10 0 5 0 12 2 1 12 6 0 12 29 11 5 2 1 16 8 11 21 23 24 25 11 Multiplier[4:0] 178 Product[9:0] Exp_Value 11 21 26 231 189 242 200 253 264 Error 8.27 (a) // Test bench for exhaustive simulation module t_Sequential_Binary_Multiplier; parameter dp_width = 5; // Width of datapath wire [2 * dp_width - 1: 0] Product; wire Ready; reg [dp_width - 1: 0] Multiplicand, Multiplier; reg Start, clock, reset_b; Sequential_Binary_Multiplier M0 (Product, Ready, Multiplicand, Multiplier, Start, clock, reset_b); initial #109200 $finish; initial begin clock = 0; #5 forever #5 clock = ~clock; end initial fork reset_b = 1; #2 reset_b = 0; #3 reset_b = 1; join initial begin #5 Start = 1; end initial begin #5 Multiplicand = 0; Multiplier = 0; repeat (31) #10 begin Multiplier = Multiplier + 1; repeat (32) @ (posedge M0.Ready) #5 Multiplicand = Multiplicand + 1; end Start = 0; end // Error Checker Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 297 reg Error; reg [2*dp_width -1: 0] Exp_Value; always @ (posedge Ready) begin Exp_Value = Multiplier * Multiplicand; //Exp_Value = Multiplier * Multiplicand + 1; Error = (Exp_Value ^ Product); end endmodule // Inject error to verify detection module Sequential_Binary_Multiplier (Product, Ready, Multiplicand, Multiplier, Start, clock, reset_b); // Default configuration: 5-bit datapath parameter dp_width = 5; // Set to width of datapath output [2*dp_width - 1: 0] Product; output Ready; input [dp_width - 1: 0] Multiplicand, Multiplier; input Start, clock, reset_b; parameter parameter reg reg reg reg reg BC_size = S_idle = S_add = S_shift = [2: 0] [dp_width - 1: 0] [BC_size - 1: 0] 3; // Size of bit counter 3'b001, // one-hot code 3'b010, 3'b100; state, next_state; A, B, Q; // Sized for datapath C; P; Load_regs, Decr_P, Add_regs, Shift_regs; // Miscellaneous combinational logic assign wire wire Product = {C, A, Q}; Zero = (P == 0); // counter is zero Ready = (state == S_idle); // controller status // control unit always @ (posedge clock, negedge reset_b) if (~reset_b) state <= S_idle; else state <= next_state; always @ (state, Start, Q[0], Zero) begin next_state = S_idle; Load_regs = 0; Decr_P = 0; Add_regs = 0; Shift_regs = 0; case (state) S_idle: begin if (Start) next_state = S_add; Load_regs = 1; end S_add: begin next_state = S_shift; Decr_P = 1; if (Q[0]) Add_regs = 1; end S_shift: begin Shift_regs = 1; if (Zero) next_state = S_idle; else next_state = S_add; end default: next_state = S_idle; endcase end Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 298 // datapath unit always @ (posedge clock) begin if (Load_regs) begin P <= dp_width; A <= 0; C <= 0; B <= Multiplicand; Q <= Multiplier; end if (Add_regs) {C, A} <= A + B; if (Shift_regs) {C, A, Q} <= {C, A, Q} >> 1; if (Decr_P) P <= P -1; end endmodule Sample of simulation results: Name 99539 99579 99619 99659 clock reset_b Start state[2:0] 4 1 2 4 2 4 2 4 2 4 2 4 1 2 4 5 4 Load_regs Decr_P Add_regs Shift_regs Zero 0 P[2:0] 4 3 2 08 B[4:0] A[4:0] 5 1 0 09 0e 07 11 08 00 09 04 02 0b 0a 05 0e 07 10 08 00 C Q[4:0] Multiplicand[4:0] 1d 1e 0f 8 0b 05 1d 9 10 29 Multiplier[4:0] Product[9:0] 17 465 232 29 317 158 79 367 183 471 235 523 261 29 Ready Exp_Value[9:0] 203 232 261 Error Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 299 (b) In this part the controller is described by Fig. 8.18. The test bench includes probes to display the state of the controller. // Test bench for exhaustive simulation module t_Sequential_Binary_Multiplier; parameter dp_width = 5; // Width of datapath wire [2 * dp_width - 1: 0] Product; wire Ready; reg [dp_width - 1: 0] Multiplicand, Multiplier; reg Start, clock, reset_b; Sequential_Binary_Multiplier M0 (Product, Ready, Multiplicand, Multiplier, Start, clock, reset_b); initial #109200 $finish; initial begin clock = 0; #5 forever #5 clock = ~clock; end initial fork reset_b = 1; #2 reset_b = 0; #3 reset_b = 1; join initial begin #5 Start = 1; end initial begin #5 Multiplicand = 0; Multiplier = 0; repeat (31) #10 begin Multiplier = Multiplier + 1; repeat (32) @ (posedge M0.Ready) #5 Multiplicand = Multiplicand + 1; end Start = 0; end // Error Checker reg Error; reg [2*dp_width -1: 0] Exp_Value; always @ (posedge Ready) begin Exp_Value = Multiplier * Multiplicand; //Exp_Value = Multiplier * Multiplicand + 1; Error = (Exp_Value ^ Product); end // Inject error to verify detection wire [2: 0] state = {M0.G2, M0.G1, M0.G0}; endmodule module Sequential_Binary_Multiplier (Product, Ready, Multiplicand, Multiplier, Start, clock, reset_b); // Default configuration: 5-bit datapath parameter dp_width = 5; // Set to width of datapath output [2*dp_width - 1: 0] Product; output Ready; input [dp_width - 1: 0] Multiplicand, Multiplier; input Start, clock, reset_b; parameter reg [dp_width - 1: 0] reg reg [BC_size - 1: 0] wire BC_size = 3; // Size of bit counter A, B, Q; // Sized for datapath C; P; Load_regs, Decr_P, Add_regs, Shift_regs; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 300 // Status signals assign wire wire Product = {C, A, Q}; Zero = (P == 0); Q0 = Q[0]; // counter is zero // One-Hot Control unit (See Fig. 8.18) DFF_S M0 (G0, D0, clock, Set); DFF M1 (G1, D1, clock, reset_b); DFF M2 (G2, G1, clock, reset_b); or (D0, w1, w2); and (w1, G0, Start_b); and (w2, Zero, G2); not (Start_b, Start); not (Zero_b, Zero); or (D1, w3, w4); and (w3, Start, G0); and (w4, Zero_b, G2); and (Load_regs, G0, Start); and (Add_regs, Q0, G1); assign Ready = G0; assign Decr_P = G1; assign Shift_regs = G2; not (Set, reset_b); // datapath unit always @ (posedge clock) begin if (Load_regs) begin P <= dp_width; A <= 0; C <= 0; B <= Multiplicand; Q <= Multiplier; end if (Add_regs) {C, A} <= A + B; if (Shift_regs) {C, A, Q} <= {C, A, Q} >> 1; if (Decr_P) P <= P -1; end endmodule module DFF_S (output reg Q, input data, clock, Set); always @ ( posedge clock, posedge Set) if (Set) Q <= 1'b1; else Q<= data; endmodule module DFF (output reg Q, input data, clock, reset_b); always @ ( posedge clock, negedge reset_b) if (reset_b == 0) Q <= 1'b0; else Q<= data; endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 301 Sample of simulation results: ts: Name 40699 40739 40779 40819 clock reset_b Start state[2:0] 1 2 0 5 4 2 4 2 4 2 4 2 4 1 2 4 5 4 Load_regs Decr_P Add_regs Shift_regs P[2:0] 4 3 2 1 0 Zero B[4:0] 11 A[4:0] 06 12 00 12 13 09 1b 0d 06 00 10 18 0c C 0c Q[4:0] Multiplicand[4:0] 06 03 17 18 19 12 Multiplier[4:0] Product[9:0] 01 204 12 6 3 579 289 865 432 216 12 Ready Exp_Value[9:0] 204 216 Error 8.28 // Test bench for exhaustive simulation module t_Sequential_Binary_Multiplier; parameter dp_width = 5; // Width of datapath wire [2 * dp_width - 1: 0] Product; wire Ready; reg [dp_width - 1: 0] Multiplicand, Multiplier; reg Start, clock, reset_b; Sequential_Binary_Multiplier M0 (Product, Ready, Multiplicand, Multiplier, Start, clock, reset_b); initial #109200 $finish; initial begin clock = 0; #5 forever #5 clock = ~clock; end initial fork reset_b = 1; #2 reset_b = 0; #3 reset_b = 1; join initial begin #5 Start = 1; end Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 302 initial begin #5 Multiplicand = 0; Multiplier = 0; repeat (31) #10 begin Multiplier = Multiplier + 1; repeat (32) @ (posedge M0.Ready) #5 Multiplicand = Multiplicand + 1; end Start = 0; end // Error Checker reg Error; reg [2*dp_width -1: 0] Exp_Value; always @ (posedge Ready) begin Exp_Value = Multiplier * Multiplicand; //Exp_Value = Multiplier * Multiplicand + 1; // Inject error to verify detection Error = (Exp_Value ^ Product); end wire [2: 0] state = {M0.M0.G2, M0.M0.G1, M0.M0.G0}; // Watch state endmodule module Sequential_Binary_Multiplier #(parameter dp_width = 5) ( output [2*dp_width -1: 0] Product, output Ready, input [dp_width -1: 0] Multiplicand, Multiplier, input Start, clock, reset_b ); wire Load_regs, Decr_P, Add_regs, Shift_regs, Zero, Q0; Controller M0 (Ready, Load_regs, Decr_P, Add_regs, Shift_regs, Start, Zero, Q0, clock, reset_b); Datapath M1(Product, Q0, Zero,Multiplicand, Multiplier, Start, Load_regs, Decr_P, Add_regs, Shift_regs, clock, reset_b); endmodule module Controller ( output Ready, output Load_regs, Decr_P, Add_regs, Shift_regs, input Start, Zero, Q0, clock, reset_b ); // One-Hot Control unit (See Fig. 8.18) DFF_S M0 (G0, D0, clock, Set); DFF M1 (G1, D1, clock, reset_b); DFF M2 (G2, G1, clock, reset_b); or (D0, w1, w2); and (w1, G0, Start_b); and (w2, Zero, G2); not (Start_b, Start); not (Zero_b, Zero); or (D1, w3, w4); and (w3, Start, G0); and (w4, Zero_b, G2); and (Load_regs, G0, Start); and (Add_regs, Q0, G1); assign Ready = G0; assign Decr_P = G1; assign Shift_regs = G2; not (Set, reset_b); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 303 module Datapath #(parameter dp_width = 5, BC_size = 3) ( output [2*dp_width - 1: 0] Product, output Q0, output Zero, input [dp_width - 1: 0] Multiplicand, Multiplier, input Start, Load_regs, Decr_P, Add_regs, Shift_regs, clock, reset_b ); reg [dp_width - 1: 0] A, B, Q; // Sized for datapath reg C; reg [BC_size - 1: 0] P; assign Product = {C, A, Q}; // Status signals assign Zero = (P == 0); // counter is zero assign Q0 = Q[0]; always @ (posedge clock) begin if (Load_regs) begin P <= dp_width; A <= 0; C <= 0; B <= Multiplicand; Q <= Multiplier; end if (Add_regs) {C, A} <= A + B; if (Shift_regs) {C, A, Q} <= {C, A, Q} >> 1; if (Decr_P) P <= P -1; end endmodule module DFF_S (output reg Q, input data, clock, Set); always @ ( posedge clock, posedge Set) if (Set) Q <= 1'b1; else Q<= data; endmodule module DFF (output reg Q, input data, clock, reset_b); always @ ( posedge clock, negedge reset_b) if (reset_b == 0) Q <= 1'b0; else Q<= data; endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 304 Name 58738 58778 58818 58858 clock reset_b Start state[2:0] 1 2 0 5 4 2 4 2 4 2 4 2 4 1 2 4 5 4 Load_regs Decr_P Add_regs Shift_regs P[2:0] 4 3 2 1 0 Q0 Zero B[4:0] 15 16 17 C A[4:0] 0b Q[4:0] 05 Multiplicand[4:0] 00 16 11 0b 05 02 08 14 1a 21 17 0d 0b 00 16 11 22 23 17 Multiplier[4:0] Product[9:0] 01 357 17 721 360 180 90 45 749 374 17 Ready 357 Exp_Value[9:0] 374 Error 8.29 (a) Inputs: xyEF 00-S0 01-1--- S1 S2 ---1 S3 S4 --0- S7 S6 --1- S5 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 305 (b) DS0 = x'y'S0 + S3 + S5 +S7 DS1 = xS0 DS2 = x'yS0 + S1 DS3 = FS2 DS4 = F'S2 DS5 = E'S5 DS6 = E'S4 DS7 = S6 (c) Present state Output G G G 1 2 3 Inputs x y E F Next state G1 G2 G3 S0 S0 S0 0 0 0 0 0 0 0 0 0 0 0 x x 1 x x x 0 1 x x 0 0 0 0 0 1 0 1 0 S1 0 0 1 x x x x 0 1 0 S2 S2 0 1 0 0 1 0 x x 0 x x x 1 x 1 0 0 0 1 1 S3 0 1 1 x x x x 0 0 0 S4 S4 1 0 0 1 0 0 x x x 0 x x x 1 1 1 0 1 0 1 S5 1 0 1 x x x x 0 0 0 S6 1 1 0 x x x x 1 1 0 S7 1 1 1 x x x x 0 0 0 (d) DG1 D Q Q' DG2 D Q Q' DG3 D Q S0 S1 S2 S3 S4 S5 S6 S7 Q' Clock Reset DG1 = F'S2 + S4 + S6 DG2 = x'yS0 + S1 + FS2 + E'S4 + S6 DG3 = xS0 + FS2 + ES4 + S6 (e) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 306 Present state G1 G2 G3 Next state G1 G2 G3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 x'y' x x'y 0 0 1 0 1 0 0 1 0 0 1 0 Input conditions Mux1 Mux2 Mux3 0 x'y x None 0 1 0 1 0 0 0 1 1 F' F' F' F F 0 1 1 0 0 0 None 0 0 0 1 0 0 1 0 0 1 1 0 1 0 1 E' E' 1 E' E 1 0 1 0 0 0 None 0 0 0 1 1 0 1 1 0 None 1 1 1 1 1 1 0 0 0 None 0 0 0 (f) F' 0 1 x' y F E' 1 0 x 0 F E 1 0 s2 s1 s0 1 8x1 2 3 Mux 4 5 6 7 D Q G3 Q' 0 s2 s1 s0 1 2 8x1 3 4 Mux 5 6 7 D 0 s2 s1 s0 1 2 8x1 3 4 Mux 5 6 7 D S0 S1 Q G2 Q' Q 3 x 8 S2 S Decoder S34 S5 S6 S7 G1 Q' Clock reset_b (g) module Controller_8_29g (input x, y, E, F, clock, reset_b); supply0 GND; supply1 VCC; mux_8x1 M3 (m3, GND, GND, F_bar, GND, VCC, GND, VCC, GND, G3, G2, G1); mux_8x1 M2 (m2, w1, VCC, F, GND, E_bar, GND, VCC, GND, G3, G2, G1); mux_8x1 M1 (m1, x, GND, F, GND, E, GND, VCC, GND, G3, G2, G1); DFF_8_28g DM3 (G3, m3, clock, reset_b); DFF_8_28g DM2 (G2, m2, clock, reset_b); DFF_8_28g DM1 (G1, m1, clock, reset_b); decoder_3x8 M0_D (y0, y1, y2, y3, y4, y5, y6, y7, G3, G2, G1); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 307 and (w1, x_bar, y); not (F_bar, F); not (E_bar, E); not (x_bar, x); endmodule // Test plan: Exercise all paths of the ASM chart module t_Controller_8_29g (); reg x, y, E, F, clock, reset_b; Controller_8_29g M0 (x, y, E, F, clock, reset_b); wire [2: 0] state = {M0.G3, M0.G2, M0.G1}; initial #500 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin end initial fork reset_b = 0; #2 reset_b = 1; #0 begin x = 1; y = 1; E = 1; F = 1; end // Path: S_0, S_1, S_2, S_34 #80 reset_b = 0; #92 reset_b = 1; #90 begin x = 1; y = 1; E = 1; F = 0; end #150 reset_b = 0; #152 reset_b = 1; #150 begin x = 1; y = 1; E = 0; F = 0; end // Path: S_0, S_1, S_2, S_4, S_5 #200 reset_b = 0; #202 reset_b = 1; #190 begin x = 1; y = 1; E = 0; F = 0; end // Path: S_0, S_1, S_2, S_4, S_6, S_7 #250 reset_b = 0; #252 reset_b = 1; #240 begin x = 0; y = 0; E = 0; F = 0; end // Path: S_0 #290 reset_b = 0; #292 reset_b = 1; #280 begin x = 0; y = 1; E = 0; F = 0; end // Path: S_0, S_2, S_4, S_6, S_7 #360 reset_b = 0; #362 reset_b = 1; #350 begin x = 0; y = 1; E = 1; F = 0; end // Path: S_0, S_2, S_4, S_5 #420 reset_b = 0; #422 reset_b = 1; #410 begin x = 0; y = 1; E = 0; F = 1; end // Path: S_0, S_2, S_3 join endmodule module mux_8x1 (output reg y, input x0, x1, x2, x3, x4, x5, x6, x7, s2, s1, s0); always @ (x0, x1, x2, x3, x4, x5, x6, x7, s0, s1, s2) case ({s2, s1, s0}) 3'b000: y = x0; 3'b001: y = x1; 3'b010: y = x2; 3'b011: y = x3; 3'b100: y = x4; 3'b101: y = x5; 3'b110: y = x6; 3'b111: y = x7; endcase endmodule module DFF_8_28g (output reg q, input data, clock, reset_b); always @ (posedge clock, negedge reset_b) if (!reset_b) q <= 1'b0; else q <= data; endmodule module decoder_3x8 (output reg y0, y1, y2, y3, y4, y5, y6, y7, input x2, x1, x0); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 308 always @ (x0, x1, x2) begin {y7, y6, y5, y4, y3, y2, y1, y0} = 8'b0; case ({x2, x1, x0}) 3'b000: y0= 1'b1; 3'b001: y1= 1'b1; 3'b010: y2= 1'b1; 3'b011: y3= 1'b1; 3'b100: y4= 1'b1; 3'b101: y5= 1'b1; 3'b110: y6= 1'b1; 3'b111: y7= 1'b1; endcase end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 309 Path: S_0, S_1, S_2, S_3 and Path: S_0, S_1, S_2, S_4, S_5 Name 0 30 60 90 120 clock reset_b x y E F state[2:0] 0 1 2 3 0 1 2 3 0 1 2 4 5 0 Path: S_0, S_1, S_2, S_4, S_6, S_7 Name 120 150 180 210 240 clock reset_b x y E F state[2:0] 4 5 0 1 0 1 2 4 6 7 0 1 2 4 6 7 0 Path: S_0 and Path , S_0, S_2, S_4, S_6, S_7 Name 240 270 300 330 360 clock reset_b x y E F state[2:0] 6 7 0 2 0 2 4 6 7 0 2 4 0 2 4 Path: S_0, S_2, S_4, S_5 and path S_0, S_2, S_3 Name 324 354 384 414 444 clock reset_b x y E F state[2:0] 7 0 2 4 0 2 4 5 0 2 3 0 2 3 0 (h) module Controller_8_29h (input x, y, E, F, clock, reset_b); parameter S_0 = 3'b000, S_1 = 3'b001, S_2 = 3'b010, S_3 = 3'b011, S_4 = 3'b100, S_5 = 3'b101, S_6 = 3'b110, S_7 = 3'b111; reg [2: 0 ] state, next_state; always @ (posedge clock, negedge reset_b) if (!reset_b) state <= S_0; else state <= next_state; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 2 310 always @ (state, x, y, E, F) begin case (state) S_0: if (x) next_state = S_1; else next_state = y ? S_2: S_0; S_1: next_state = S_2; S_2: if (F) next_state = S_3; else next_state = S_4; S_3, S_5, S_7: next_state = S_0; S_4: if (E) next_state = S_5; else next_state = S_6; S_6: next_state = S_7; default: next_state = S_0; endcase end endmodule // Test plan: Exercise all paths of the ASM chart module t_Controller_8_29h (); reg x, y, E, F, clock, reset_b; Controller_8_29h M0 (x, y, E, F, clock, reset_b); initial #500 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin end initial fork reset_b = 0; #2 reset_b = 1; #20 begin x = 1; y = 1; E = 1; F = 1; end // Path: S_0, S_1, S_2, S_34 #80 reset_b = 0; #92 reset_b = 1; #90 begin x = 1; y = 1; E = 1; F = 0; end #150 reset_b = 0; #152 reset_b = 1; #150 begin x = 1; y = 1; E = 0; F = 0; end // Path: S_0, S_1, S_2, S_4, S_5 #200 reset_b = 0; #202 reset_b = 1; #190 begin x = 1; y = 1; E = 0; F = 0; end // Path: S_0, S_1, S_2, S_4, S_6, S_7 #250 reset_b = 0; #252 reset_b = 1; #240 begin x = 0; y = 0; E = 0; F = 0; end // Path: S_0 #290 reset_b = 0; #292 reset_b = 1; #280 begin x = 0; y = 1; E = 0; F = 0; end // Path: S_0, S_2, S_4, S_6, S_7 #360 reset_b = 0; #362 reset_b = 1; #350 begin x = 0; y = 1; E = 1; F = 0; end // Path: S_0, S_2, S_4, S_5 #420 reset_b = 0; #422 reset_b = 1; #410 begin x = 0; y = 1; E = 0; F = 1; end // Path: S_0, S_2, S_3 join endmodule Note: Simulation results match those for 8.39g. 8.30 8.31 (a) E = 1 (b) E = 0 A = 0110, B = 0010, C = 0000. A * B = 1100 A | B = 0110 A + B = 1000 A ∧ B = 0100 A – B = 0100 &A = 0 ~ C = 1111 ~|C = 1 A & B = 0010 A || B = 1 A && C = 0 |A=1 AB=1 A != B = 1 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 311 8.32 4 + S1 4-bit Counter select S2 4 R1 count load R2 4 Mux select = S1 load = S1 + S'1S'2 count = S'1S2 clock 8.33 Assume that the states are encoded one-hot as T0, T1, T2, T3. The select lines of the mux are generated as: s1 = T2 + T3 s0 = T1 + T3 The signal to load R4 can be generated by the host processor or by: load = T0 + T1 + T2 + T3. R1 R2 R3 T0 T1 T2 T3 8 8 8 8 0 1 8 Mux Register 8 R4 2 3 s1 s0 load R0 4x2 Encoder load clock 8.34 (a) module Datapath_BEH #(parameter dp_width = 8, R2_width = 4) ( output [R2_width -1: 0] count, output reg E, output Zero, input [dp_width -1: 0] data, input Load_regs, Shift_left, Incr_R2, clock, reset_b); reg [dp_width -1: 0] R1; reg [R2_width -1: 0] R2; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 312 assign count = R2; assign Zero = ~(| R1); always @ (posedge clock) begin E <= R1[dp_width -1] & Shift_left; if (Load_regs) begin R1 <= data; R2 <= {R2_width{1'b1}}; end if (Shift_left) {E, R1} <= {E, R1} << 1; if (Incr_R2) R2 <= R2 + 1; end endmodule // Test Plan for Datapath Unit: // Demonstrate action of Load_regs // R1 gets data, R2 gets all ones // Demonstrate action of Incr_R2 // Demonstrate action of Shift_left and detect E // Test bench for datapath module t_Datapath_Unit #(parameter dp_width = 8, R2_width = 4) ( ); wire [R2_width -1: 0] count; wire E, Zero; reg [dp_width -1: 0] data; reg Load_regs, Shift_left, Incr_R2, clock, reset_b; Datapath_BEH M0 (count, E, Zero, data, Load_regs, Shift_left, Incr_R2, clock, reset_b); initial #250 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin reset_b = 0; #2 reset_b = 1; end initial fork data = 8'haa; Load_regs = 0; Incr_R2 = 0; Shift_left = 0; #10 Load_regs = 1; #20 Load_regs = 0; #50 Incr_R2 = 1; #120 Incr_R2 = 0; #90 Shift_left = 1; #200 Shift_left = 0; join endmodule Note: The simulation results show tests of the operations of the datapath independent of the control unit, so count does not represent the number of ones in the data. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 313 R1gets data and R2 gets all ones Name 0 60 120 180 clock reset_b R2 increments while Incr_R2 is asserted R1 shifts left Zero asserts Load_regs Incr_R2 Shift_left Note that E matches previous value of R1[7] Zero E aa data[7:0] R1[7:0] xx aa 54 a8 50 a0 40 80 00 R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] R2[3:0] x f 0 1 2 3 4 5 6 count[3:0] x f 0 1 2 3 4 5 6 (b) // Control Unit module Controller_BEH ( output Ready, output reg Load_regs, output Incr_R2, Shift_left, input Start, Zero, E, clock, reset_b ); parameter S_idle = 0, S_1 = 1, S_2 = 2, S_3 = 3; reg [1:0] state, next_state; assign Ready = (state == S_idle); assign Incr_R2 = (state == S_1); assign Shift_left = (state == S_2); always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= S_idle; else state <= next_state; always @ (state, Start, Zero, E) begin Load_regs = 0; case (state) S_idle: if (Start) begin Load_regs = 1; next_state = S_1; end else next_state = S_idle; S_1: if (Zero) next_state = S_idle; else next_state = S_2; S_2: S_3: endcase end endmodule next_state = S_3; if (E) next_state = S_1; else next_state = S_2; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 314 // Test plan for Control Unit // Verify that state enters S_idle with reset_b asserted. // With reset_b de-asserted, verify that state enters S_1 and asserts Load_Regs when // Start is asserted. // Verify that Incr_R2 is asserted in S_1. // Verify that state returns to S_idle from S_1 if Zero is asserted. // Verify that state goes to S_2 if Zero is not asserted. // Verify that Shift_left is asserted in S_2. // Verify that state goes to S_3 from S_2 unconditionally. // Verify that state returns to S_2 from S_3 id E is not asserted. // Verify that state goes to S_1 from S_3 if E is asserted. // Test bench for Control Unit module t_Control_Unit (); wire Ready, Load_regs, Incr_R2, Shift_left; reg Start, Zero, E, clock, reset_b; Controller_BEH M0 (Ready, Load_regs, Incr_R2, Shift_left, Start, Zero, E, clock, reset_b); initial #250 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin reset_b = 0; #2 reset_b = 1; end initial fork Zero = 1; E = 0; Start = 0; #20 Start = 1; // Cycle from S_idle to S_1 #80 Start = 0; #70 Zero = 0; // S_idle to S_1 to S_2 to S_3 and cycle to S_2. #130 E = 1; // Cycle to S_3 to S_1 to S_2 to S_3 #150 Zero = 1; // Return to S_idle join endmodule Go to S_1 and cyle to S_idle while Zero = 1 Name Go to S_2 and cyle to S_3 while E = 0 0 Go to S_1 and cyle to S_3 while Zero = 0 Return to S_idle 70 140 210 clock reset_b Start Zero E state[1:0] 0 1 0 1 0 1 2 3 2 3 2 3 1 2 3 1 0 Ready Load_regs Incr_R2 Shift_left Ready asserts while Load_regs asserts while Incr_R2 asserts while state = S_1 state = S_idle state = S_idle and Start = 1 Shift_left asserts while state = S_2 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 315 (c) // Integrated system module Count_Ones_BEH_BEH # (parameter dp_width = 8, R2_width = 4) ( output [R2_width -1: 0] count, input [dp_width -1: 0] data, input Start, clock, reset_b ); wire Load_regs, Incr_R2, Shift_left, Zero, E; Controller_BEH M0 (Ready, Load_regs, Incr_R2, Shift_left, Start, Zero, E, clock, reset_b); Datapath_BEH M1 (count, E, Zero, data, Load_regs, Shift_left, Incr_R2, clock, reset_b); endmodule // Test plan for integrated system // Test for data values of 8'haa, 8'h00, 8'hff. // Test bench for integrated system module t_count_Ones_BEH_BEH (); parameter dp_width = 8, R2_width = 4; wire [R2_width -1: 0] count; reg [dp_width -1: 0] data; reg Start, clock, reset_b; Count_Ones_BEH_BEH M0 (count, data, Start, clock, reset_b); initial #700 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin reset_b = 0; #2 reset_b = 1; end initial fork data = 8'haa; // Expect count = 4 Start = 0; #20 Start = 1; #30 Start = 0; #40 data = 8'b00; // Expect count = 0 #250 Start = 1; #260 Start = 0; #280 data = 8'hff; #280 Start = 1; #290 Start = 0; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 316 Name 0 70 140 210 clock reset_b Ready Start Load_regs Incr_R2 Shift_left Zero E 0 state[1:0] 1 3 1 2 3 2 3 1 2 3 2 3 aa data[7:0] R1[7:0] xx R2[3:0] x count[3:0] x Name 2 1 2 3 2 3 1 0 00 aa f 54 a8 50 a0 40 80 00 0 1 2 3 4 0 1 2 3 4 188 248 308 368 clock reset_b Ready Start Load_regs Incr_R2 Shift_left Zero E state[1:0] 2 3 1 0 1 0 1 2 3 1 2 3 00 data[7:0] 2 3 1 2 3 ff 00 R1[7:0] 1 ff fe fc f8 f0 R2[3:0] 3 4 f 0 f 0 1 2 3 count[3:0] 3 4 15 0 15 0 1 2 3 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 317 Name 258 318 378 438 498 558 clock reset_b Ready Start Load_regs Incr_R2 Shift_left Zero E state[1:0] 1 2 3 1 2 3 1 2 3 1 2 3 1 f 2 3 1 2 3 1 2 3 1 2 3 1 0 ff 00 R1[7:0] count[3:0] 1 00 data[7:0] R2[3:0] 0 ff fe fc f8 f0 e0 c0 80 00 0 f 0 1 2 3 4 5 6 7 8 0 15 0 1 2 3 4 5 6 7 8 (d) // One-Hot Control unit module Controller_BEH_1Hot ( output Ready, output reg Load_regs, output Incr_R2, Shift_left, input Start, Zero, E, clock, reset_b ); parameter S_idle = 4'b001, S_1 = 4'b0010, S_2 = 4'b0100, S_3 = 4'b1000; reg [3:0] state, next_state; assign Ready = (state == S_idle); assign Incr_R2 = (state == S_1); assign Shift_left = (state == S_2); always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= S_idle; else state <= next_state; always @ (state, Start, Zero, E) begin Load_regs = 0; case (state) S_idle: if (Start) begin Load_regs = 1; next_state = S_1; end else next_state = S_idle; S_1: if (Zero) next_state = S_idle; else next_state = S_2; S_2: next_state = S_3; S_3: if (E) next_state = S_1; else next_state = S_2; endcase end endmodule Note: Test plan, test bench and simulation results are same as (b), but with states numbered with one-hot codes. (e) // Integrated system with one-hot controller module Count_Ones_BEH_1Hot Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 318 # (parameter dp_width = 8, R2_width = 4) ( output [R2_width -1: 0] count, input [dp_width -1: 0] data, input Start, clock, reset_b ); wire Load_regs, Incr_R2, Shift_left, Zero, E; Controller_BEH_1Hot M0 (Ready, Load_regs, Incr_R2, Shift_left, Start, Zero, E, clock, reset_b); Datapath_BEH M1 (count, E, Zero, data, Load_regs, Shift_left, Incr_R2, clock, reset_b); endmodule Note: Test plan, test bench and simulation results are same as (c), but with states numbered with one-hot codes. 8.35 Note: Signal Start is initialized to 0 when the simulation begins. Otherwise, the state of the structural model will become X at the first clock after the reset condition is deasserted, with Start and Load_Regs having unknown values. In this condition the structural model cannot operate correctly. 0 Name 30 60 clock reset_b Start Load_regs Shift_left Incr_R2 Zero Ready x state[1:0] 0 X data[7:0] ff count[3:0] x module Count_Ones_STR_STR (count, Ready, data, Start, clock, reset_b); // Mux – decoder implementation of control logic // controller is structural // datapath is structural parameter output output input input wire R1_size = 8, R2_size = 4; [R2_size -1: 0] count; Ready; [R1_size -1: 0] data; Start, clock, reset_b; Load_regs, Shift_left, Incr_R2, Zero, E; Controller_STR M0 (Ready, Load_regs, Shift_left, Incr_R2, Start, E, Zero, clock, reset_b); Datapath_STR M1 (count, E, Zero, data, Load_regs, Shift_left, Incr_R2, clock); endmodule module Controller_STR (Ready, Load_regs, Shift_left, Incr_R2, Start, E, Zero, clock, reset_b); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 319 output output input input input supply0 supply1 parameter wire wire wire Ready; Load_regs, Shift_left, Incr_R2; Start; E, Zero; clock, reset_b; GND; PWR; S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; // Binary code Load_regs, Shift_left, Incr_R2; G0, G0_b, D_in0, D_in1, G1, G1_b; Zero_b = ~Zero; wire E_b = ~E; wire [1:0]select = {G1, G0}; wire [0:3]Decoder_out; assign Ready = ~Decoder_out[0]; assign Incr_R2 = ~Decoder_out[1]; assign Shift_left = ~Decoder_out[2]; and (Load_regs, Ready, Start); mux_4x1_beh Mux_1 (D_in1, GND, Zero_b, PWR, E_b, select); mux_4x1_beh Mux_0 (D_in0, Start, GND, PWR, E, select); D_flip_flop_AR_b M1 (G1, G1_b, D_in1, clock, reset_b); D_flip_flop_AR_b M0 (G0, G0_b, D_in0, clock, reset_b); decoder_2x4_df M2 (Decoder_out, G1, G0, GND); endmodule module Datapath_STR (count, E, Zero, data, Load_regs, Shift_left, Incr_R2, clock); parameter R1_size = 8, R2_size = 4; output [R2_size -1: 0] count; output E, Zero; input [R1_size -1: 0] data; input Load_regs, Shift_left, Incr_R2, clock; wire [R1_size -1: 0] R1; supply0 Gnd; supply1 Pwr; assign Zero = (R1 == 0); Shift_Reg Counter D_flip_flop_AR and ( endmodule M1 M2 M3 (R1, data, Gnd, Shift_left, Load_regs, clock, Pwr); (count, Load_regs, Incr_R2, clock, Pwr); (E, w1, clock, Pwr); w1, R1[R1_size -1], Shift_left); module Shift_Reg (R1, data, SI_0, Shift_left, Load_regs, clock, reset_b); parameter R1_size = 8; output [R1_size -1: 0] R1; input [R1_size -1: 0] data; input SI_0, Shift_left, Load_regs; input clock, reset_b; reg [R1_size -1: 0] R1; always @ (posedge clock, negedge reset_b) if (reset_b == 0) R1 <= 0; else begin if (Load_regs) R1 <= data; else if (Shift_left) R1 <= {R1[R1_size -2:0], SI_0}; end endmodule module Counter (R2, Load_regs, Incr_R2, clock, reset_b); parameter R2_size = 4; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 320 output [R2_size -1: 0] input input reg [R2_size -1: 0] R2; Load_regs, Incr_R2; clock, reset_b; R2; always @ (posedge clock, negedge reset_b) if (reset_b == 0) R2 <= 0; else if (Load_regs) R2 <= {R2_size {1'b1}}; // Fill with 1 else if (Incr_R2 == 1) R2 <= R2 + 1; endmodule module D_flip_flop_AR (Q, D, CLK, RST); output Q; input D, CLK, RST; reg Q; always @ (posedge CLK, negedge RST) if (RST == 0) Q <= 1'b0; else Q <= D; endmodule module D_flip_flop_AR_b (Q, Q_b, D, CLK, RST); output Q, Q_b; input D, CLK, RST; reg Q; assign Q_b = ~Q; always @ (posedge CLK, negedge RST) if (RST == 0) Q <= 1'b0; else Q <= D; endmodule // Behavioral description of 4-to-1 line multiplexer // Verilog 2005 port syntax module mux_4x1_beh ( output reg m_out, input in_0, in_1, in_2, in_3, input [1: 0] select ); always @ (in_0, in_1, in_2, in_3, select) // Verilog 2005 syntax case (select) 2'b00: m_out = in_0; 2'b01: m_out = in_1; 2'b10: m_out = in_2; 2'b11: m_out = in_3; endcase endmodule // Dataflow description of 2-to-4-line decoder // See Fig. 4.19. Note: The figure uses symbol E, but the // Verilog model uses enable to clearly indicate functionality. module decoder_2x4_df (D, A, B, enable); output [0: 3] D; input input A, B; enable; assign D[0] = ~(~A & ~B & ~enable), D[1] = ~(~A & B & ~enable), D[2] = ~(A & ~B & ~enable), Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 321 D[3] = ~(A & B & ~enable); endmodule module t_Count_Ones; parameter R1_size = 8, R2_size = 4; wire [R2_size -1: 0] R2; wire [R2_size -1: 0] count; wire Ready; reg [R1_size -1: 0] data; reg Start, clock, reset_b; wire [1: 0] state; // Use only for debug assign state = {M0.M0.G1, M0.M0.G0}; Count_Ones_STR_STR M0 (count, Ready, data, Start, clock, reset_b); initial #4000 $finish; initial begin clock = 0; #5 forever #5 clock = ~clock; end initial fork Start = 0; #1 reset_b = 1; #3 reset_b = 0; #4 reset_b = 1; data = 8'Hff; # 25 Start = 1; # 35 Start = 0; #310 data = 8'h0f; #310 Start = 1; #320 Start = 0; #610 data = 8'hf0; #610 Start = 1; #620 Start = 0; #910 data = 8'h00; #910 Start = 1; #920 Start = 0; #1210 data = 8'haa; #1210 Start = 1; #1220 Start = 0; #1510 data = 8'h0a; #1510 Start = 1; #1520 Start = 0; #1810 data = 8'ha0; #1810 Start = 1; #1820 Start = 0; #2110 data = 8'h55; #2110 Start = 1; #2120 Start = 0; #2410 data = 8'h05; #2410 Start = 1; #2420 Start = 0; #2710 data = 8'h50; #2710 Start = 1; #2720 Start = 0; #3010 data = 8'ha5; #3010 Start = 1; #3020 Start = 0; #3310 data = 8'h5a; #3310 Start = 1; #3320 Start = 0; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 322 Name 2184 2324 2464 2604 2744 2884 clock reset_b Start Load_regs Shift_left Incr_R2 Zero Ready 0 state[1:0] 55 data[7:0] count[3:0] 8.36 0 1 2 0 05 3 4 0 50 1 2 0 1 2 Note: See Prob. 8.35 for a behavioral model of the datapath unit, Prob. 8.36d for a one-hot control unit. (a) T0, T1, T2, T3 be asserted when the state is in S_idle, S_1, S_2, and S_3, respectively. Let D0, D1, D2, and D3 denote the inputs to the one-hot flip-flops. D0 = T0 Start' + T1 Zero D1 = T0 Start + T3 E D2 = T1 Zero' + T3 E' D3 = T2 (b) Gate-level one-hot controller module Controller_Gates_1Hot ( output Ready, output Load_regs, Incr_R2, Shift_left, input Start, Zero, E, clock, reset_b ); wire w1, w2, w3, w4, w5, w6; wire T0, T1, T2, T3; wire set; assign Ready = T0; assign Incr_R2 = T1; assign Shift_left = T2; and (Load_regs, T0, Start); not (set, reset_b); DFF_S M0 (T0, D0, clock, set); // Note: reset action must initialize S_idle = 4'b0001 DFF M1 (T1, D1, clock, reset_b); DFF M2 (T2, D2, clock, reset_b); DFF M3 (T3, D3, clock, reset_b); not (Start_b, Start); and (w1, T0, Start_b); and (w2, T1, Zero); or (D0, w1, w2); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 323 and (w3, T0, Start); and (w4, T3, E); or (D1, w3, w4); not (Zero_b, Zero); not (E_b, E); and (w5, T1, Zero_b); and (w6, T3, E_b); or (D2, w5, w6); buf (D3, T2); endmodule module DFF (output reg Q, input D, clock, reset_b); always @ (posedge clock, negedge reset_b) if (reset_b == 0) Q <= 0; else Q <= D; endmodule module DFF_S (output reg Q, input D, clock, set); always @ (posedge clock, posedge set) if (set == 1) Q <= 1; else Q <= D; endmodule (c) // Test plan for Control Unit // Verify that state enters S_idle with reset_b asserted. // With reset_b de-asserted, verify that state enters S_1 and asserts Load_Regs when // Start is asserted. // Verify that Incr_R2 is asserted in S_1. // Verify that state returns to S_idle from S_1 if Zero is asserted. // Verify that state goes to S_2 if Zero is not asserted. // Verify that Shift_left is asserted in S_2. // Verify that state goes to S_3 from S_2 unconditionally. // Verify that state returns to S_2 from S_3 id E is not asserted. // Verify that state goes to S_1 from S_3 if E is asserted. // Test bench for One-Hot Control Unit module t_Control_Unit (); wire Ready, Load_regs, Incr_R2, Shift_left; reg Start, Zero, E, clock, reset_b; wire [3: 0] state = {M0.T3, M0.T2, M0.T1, M0.T0}; // Observe one-hot state bits Controller_Gates_1Hot M0 (Ready, Load_regs, Incr_R2, Shift_left, Start, Zero, E, clock, reset_b); initial #250 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin reset_b = 0; #2 reset_b = 1; end initial fork Zero = 1; E = 0; Start = 0; #20 Start = 1; // Cycle from S_idle to S_1 #80 Start = 0; #70 Zero = 0; // S_idle to S_1 to S_2 to S_3 and cycle to S_2. #130 E = 1; // Cycle to S_3 to S_1 to S_2 to S_3 #150 Zero = 1; // Return to S_idle join endmodule Note: simulation results match those for Prob. 8.34(d). See Prob. 8.34(c) for annotations. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 324 0 Name 60 120 180 Default clock reset_b Start Zero E 1 state[3:0] 2 1 2 1 2 4 8 4 8 4 8 2 4 8 2 1 Ready Load_regs Incr_R2 Shift_left (d) Datapath unit detail: s1 = Shift_regs + Load_regs' Shift_regs' s0 = Load_regs + Load_regs' Shift_regs' Zero 8 R1 0 8 data 1 8 R1 << 1 8 R1 4x1 Mux 2 3 8 s1 s0 Register (D-type Flipflops) 8 R1 R1_7 D Q E Q' Shift_regs clk Load_regs clock 4 0 4'b0001 + 1 2x1 Mux sel Register (D-type Flipflops) R2 Incr_R2 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 325 // Datapath unit – structural model module Datapath_STR #(parameter dp_width = 8, R2_width = 4) ( output [R2_width -1: 0] count, output E, output Zero, input [dp_width -1: 0] data, input Load_regs, Shift_left, Incr_R2, clock, reset_b); supply1 pwr; supply0 gnd; wire [dp_width -1: 0] R1_Dbus, R1; wire [R2_width -1: 0] R2_Dbus; wire DR1_0, DR1_1, DR1_2, DR1_3, DR1_4, DR1_5, DR1_6, DR1_7; wire R1_0, R1_1, R1_2, R1_3, R1_4, R1_5, R1_6, R1_7; wire R2_0, R2_1, R2_2, R2_3; wire [R2_width -1: 0] R2 = {R2_3, R2_2, R2_1, R2_0}; assign count = {R2_3, R2_2, R2_1, R2_0}; assign R1 = { R1_7, R1_6, R1_5, R1_4, R1_3, R1_2, R1_1, R1_0}; assign DR1_0 = R1_Dbus[0]; assign DR1_1 = R1_Dbus[1]; assign DR1_2 = R1_Dbus[2]; assign DR1_3 = R1_Dbus[3]; assign DR1_4 = R1_Dbus[4]; assign DR1_5 = R1_Dbus[5]; assign DR1_6 = R1_Dbus[6]; assign DR1_7 = R1_Dbus[7]; nor (Zero, R1_0, R1_1, R1_2, R1_3, R1_4, R1_5, R1_6, R1_7); DFF D_E (E, R1_7, clock, pwr); DFF DF_0 (R1_0, DR1_0, clock, pwr); DFF DF_1 (R1_1, DR1_1, clock, pwr); DFF DF_2 (R1_2, DR1_2, clock, pwr); DFF DF_3 (R1_3, DR1_3, clock, pwr); DFF DF_4 (R1_4, DR1_4, clock, pwr); DFF DF_5 (R1_5, DR1_5, clock, pwr); DFF DF_6 (R1_6, DR1_6, clock, pwr); DFF DF_7 (R1_7, DR1_7, clock, pwr); // Disable reset DFF_S DR_0 (R2_0, DR2_0, clock, Load_regs); // Load_regs (set) drives R2 to all ones DFF_S DR_1 (R2_1, DR2_1, clock, Load_regs); DFF_S DR_2 (R2_2, DR2_2, clock, Load_regs); DFF_S DR_3 (R2_3, DR2_3, clock, Load_regs); assign DR2_0 = R2_Dbus[0]; assign DR2_1 = R2_Dbus[1]; assign DR2_2 = R2_Dbus[2]; assign DR2_3 = R2_Dbus[3]; wire [1: 0] sel = {Shift_left, Load_regs}; wire [dp_width -1: 0] R1_shifted = {R1_6, R1_5, R1_4, R1_3, R1_2, R1_1, R1_0, 1'b0}; wire [R2_width -1: 0] sum = R2 + 4'b0001; Mux8_4_x_1 M0 (R1_Dbus, R1, data, R1_shifted, R1, sel); Mux4_2_x_1 M1 (R2_Dbus, R2, sum, Incr_R2); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 326 module Mux8_4_x_1 #(parameter dp_width = 8) (output reg [dp_width -1: 0] mux_out, input [dp_width -1: 0] in0, in1, in2, in3, input [1: 0] sel); always @ (in0, in1, in2, in3, sel) case (sel) 2'b00: mux_out = in0; 2'b01: mux_out = in1; 2'b10: mux_out = in2; 2'b11: mux_out = in3; endcase endmodule module Mux4_2_x_1 #(parameter dp_width = 4) (output [dp_width -1: 0] mux_out, input [dp_width -1: 0] in0, in1, input sel); assign mux_out = sel ? in1: in0; endmodule // Test Plan for Datapath Unit: // Demonstrate action of Load_regs // R1 gets data, R2 gets all ones // Demonstrate action of Incr_R2 // Demonstrate action of Shift_left and detect E // Test bench for datapath module t_Datapath_Unit #(parameter dp_width = 8, R2_width = 4) ( ); wire [R2_width -1: 0] count; wire E, Zero; reg [dp_width -1: 0] data; reg Load_regs, Shift_left, Incr_R2, clock, reset_b; Datapath_STR M0 (count, E, Zero, data, Load_regs, Shift_left, Incr_R2, clock, reset_b); initial #250 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin reset_b = 0; #2 reset_b = 1; end initial fork data = 8'haa; Load_regs = 0; Incr_R2 = 0; Shift_left = 0; #10 Load_regs = 1; #20 Load_regs = 0; #50 Incr_R2 = 1; #120 Incr_R2 = 0; #90 Shift_left = 1; #200 Shift_left = 0; join endmodule // Integrated system module Count_Ones_Gates_1_Hot_STR # (parameter dp_width = 8, R2_width = 4) ( output [R2_width -1: 0] count, input [dp_width -1: 0] data, input Start, clock, reset_b ); wire Load_regs, Incr_R2, Shift_left, Zero, E; Controller_Gates_1Hot M0 (Ready, Load_regs, Incr_R2, Shift_left, Start, Zero, E, clock, reset_b); Datapath_STR M1 (count, E, Zero, data, Load_regs, Shift_left, Incr_R2, clock, reset_b); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 327 // Test plan for integrated system // Test for data values of 8'haa, 8'h00, 8'hff. // Test bench for integrated system module t_count_Ones_Gates_1_Hot_STR (); parameter dp_width = 8, R2_width = 4; wire [R2_width -1: 0] count; reg [dp_width -1: 0] data; reg Start, clock, reset_b; wire [3: 0] state = {M0.M0.T3, M0.M0.T2, M0.M0.T1, M0.M0.T0}; Count_Ones_Gates_1_Hot_STR M0 (count, data, Start, clock, reset_b); initial #700 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin reset_b = 0; #2 reset_b = 1; end initial fork data = 8'haa; // Expect count = 4 Start = 0; #20 Start = 1; #30 Start = 0; #40 data = 8'b00; // Expect count = 0 #250 Start = 1; #260 Start = 0; #280 data = 8'hff; #280 Start = 1; #290 Start = 0; join endmodule Note: The simulation results show tests of the operations of the datapath independent of the control unit, so count does not represent the number of ones in the data. Name 0 60 120 180 clock reset_b Load_regs Incr_R2 Shift_left Zero E aa data[7:0] R1[7:0] xx aa 54 a8 50 a0 40 80 00 R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] R2[3:0] x f 0 1 2 3 4 5 6 count[3:0] x f 0 1 2 3 4 5 6 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 328 Simulations results for the integrated system match those shown in Prob. 8.34(e). See those results for additional annotation. Name 0 150 300 450 600 clock reset_b Ready Start Load_regs Shift_left Incr_R2 Zero E state[3:0] 1 aa data[7:0] 8.37 1 1 1 00 54 50 ff R1[7:0] xx 40 00 ff fe fc f8 f0 e0 c0 80 R2[3:0] x f 0 1 2 3 4 f 0 f 0 1 2 3 4 5 6 7 00 8 count[3:0] x f 0 1 2 3 4 f 0 f 0 1 2 3 4 5 6 7 8 (a) ASMD chart: reset_b S_idle /Ready Start Load_regs 1 S_running 1 Zero R1 <= data R2 <= 0 R2 <= R2 + R1[0] R1 <= R1 >> 1 Add_shift (b) RTL model: module Datapath_Unit_2_Beh #(parameter dp_width = 8, R2_width = 4) ( output [R2_width -1: 0] count, output Zero, input [dp_width -1: 0] data, input Load_regs, Add_shift, clock, reset_b ); reg [dp_width -1: 0] R1; reg [R2_width -1: 0] R2; assign count = R2; assign Zero = ~|R1; always @ (posedge clock, negedge reset_b) begin Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 329 if (reset_b == 0) begin R1 <= 0; R2 <= 0; end else begin if (Load_regs) begin R1 <= data; R2 <= 0; end if (Add_shift) begin R1 <= R1 >> 1; R2 <= R2 + R1[0]; end // concurrent operations end end endmodule // Test plan for datapath unit // Verify active-low reset action // Test for action of Add_shift // Test for action of Load_regs module t_Datapath_Unit_2_Beh(); parameter R1_size = 8, R2_size = 4; wire [R2_size -1: 0] count; wire Zero; reg [R1_size -1: 0] data; reg Load_regs, Add_shift, clock, reset_b; Datapath_Unit_2_Beh M0 (count, Zero, data, Load_regs, Add_shift, clock, reset_b); initial #1000 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork #1 reset_b = 1; #3 reset_b = 0; #4 reset_b = 1; join initial fork data = 8'haa; Load_regs = 0; Add_shift = 0; #10 Load_regs = 1; #20 Load_regs = 0; #50 Add_shift = 1; #150 Add_shift = 0; join endmodule Note that the operations of the datapath unit are tested independent of the controller, so the actions of Load_regs and add_shift and the value of count do not correspond to data. Name 0 50 100 150 clock reset_b Load R1, flush R2 Load_regs R1 shifts, R2 adds Add_shift Zero aa data[7:0] R1[7:0] 00 aa 55 2a 15 0a 05 02 01 00 R2[3:0] 0 1 2 3 4 count[7:0] 0 1 2 3 4 module Controller_2_Beh ( output Ready, Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 330 output reg Load_regs, Add_shift, input Start, Zero, clock, reset_b ); parameter S_idle = 0, S_running = 1; reg state, next_state; assign Ready = (state == S_idle); always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= S_idle; else state <= next_state; always @ (state, Start, Zero) begin next_state = S_idle; Load_regs = 0; Add_shift = 0; case (state) S_idle: S_running: if (Start) begin Load_regs = 1; next_state = S_running; end if (Zero) next_state = S_idle; else begin Add_shift = 1; next_state = S_running; end endcase end endmodule module t_Controller_2_Beh (); wire Ready, Load_regs, Add_shift; reg Start, Zero, clock, reset_b; Controller_2_Beh M0 (Ready, Load_regs, Add_shift, Start, Zero, clock, reset_b); initial #250 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin reset_b = 0; #2 reset_b = 1; end initial fork Zero = 1; Start = 0; #20 Start = 1; // Cycle from S_idle to S_1 #80 Start = 0; #70 Zero = 0; // S_idle to S_1 to S_idle #90 Zero = 1; // Return to S_idle join endmodule Note: The state transitions and outputs of the controller match the ASMD chart. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 331 Name 0 50 100 150 clock reset_b Ready Start Load_regs Add_shift Zero state module Count_of_Ones_2_Beh #(parameter dp_width = 8, R2_width = 4) ( output [R2_width -1: 0] count, output Ready, input [dp_width -1: 0] data, input Start, clock, reset_b ); wire Load_regs, Add_shift, Zero; Controller_2_Beh M0 (Ready, Load_regs, Add_shift, Start, Zero, clock, reset_b); Datapath_Unit_2_Beh M1 (count, Zero, data, Load_regs, Add_shift, clock, reset_b); endmodule // Test plan for integrated system // Test for data values of 8'haa, 8'h00, 8'hff. // Test bench for integrated system module t_Count_Ones_2_Beh (); parameter dp_width = 8, R2_width = 4; wire [R2_width -1: 0] count; reg [dp_width -1: 0] data; reg Start, clock, reset_b; Count_of_Ones_2_Beh M0 (count, Ready, data, Start, clock, reset_b); initial #700 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin reset_b = 0; #2 reset_b = 1; end initial fork data = 8'haa; // Expect count = 4 Start = 0; #20 Start = 1; #30 Start = 0; #40 data = 8'b00; // Expect count = 0 #120 Start = 1; #130 Start = 0; #140 data = 8'hff; #160 Start = 1; #170 Start = 0; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 332 Name 0 60 120 180 240 clock reset_b Start Load_regs Add_shift Zero Ready state aa data[7:0] 00 00 aa 55 2a 15 0a 05 ff 07 03 01 00 R2[3:0] 0 1 2 3 4 0 1 2 3 4 5 6 7 8 count[3:0] 0 1 2 3 4 0 1 2 3 4 5 6 7 8 R1[7:0] 02 01 00 ff 7f 3f 1f 0f (c) T0, T1 are to be asserted when the state is in S_idle, S_running, respectively. Let D0, D1 denote the inputs to the one-hot flip-flops. D0 = T0 Start' + T1 Zero D1 = T0 Start + T1 E' (d) Gate-level one-hot controller module Controller_2_Gates_1Hot ( output Ready, Load_regs, Add_shift, input Start, Zero, clock, reset_b ); wire w1, w2, w3, w4; wire T0, T1; wire set; assign Ready = T0; assign Add_shift = T1; and (Load_regs, T0, Start); not (set, reset_b); DFF_S M0 (T0, D0, clock, set); // Note: reset action must initialize S_idle = 2'b01 DFF M1 (T1, D1, clock, reset_b); not (Start_b, Start); not (Zero_b, Zero); and (w1, T0, Start_b); and (w2, T1, Zero); or (D0, w1, w2); and (w3, T0, Start); and (w4, T1, Zero_b); or (D1, w3, w4); endmodule module DFF (output reg Q, input D, clock, reset_b); always @ (posedge clock, negedge reset_b) if (reset_b == 0) Q <= 0; else Q <= D; endmodule module DFF_S (output reg Q, input D, clock, set); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 333 always @ (posedge clock, posedge set) if (set == 1) Q <= 1; else Q <= D; endmodule // Test plan for Control Unit // Verify that state enters S_idle with reset_b asserted. // With reset_b de-asserted, verify that state enters S_running and asserts Load_Regs when // Start is asserted. // Verify that state returns to S_idle from S_running if Zero is asserted. // Verify that state goes to S_running if Zero is not asserted. // Test bench for One-Hot Control Unit module t_Control_Unit (); wire Ready, Load_regs, Add_shift; reg Start, Zero, clock, reset_b; wire [3: 0] state = {M0.T1, M0.T0}; // Observe one-hot state bits Controller_2_Gates_1Hot M0 (Ready, Load_regs, Add_shift, Start, Zero, clock, reset_b); initial #250 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin reset_b = 0; #2 reset_b = 1; end initial fork Zero = 1; Start = 0; #20 Start = 1; // Cycle from S_idle to S_1 #80 Start = 0; #70 Zero = 0; // S_idle to S_1 to S_idle #90 Zero = 1; // Return to S_idle join endmodule Simulation results show that the controller matches the ASMD chart. Name 0 60 120 180 clock reset_b Start Zero Load_regs Add_shift Zero Ready state[3:0] 1 2 1 2 1 2 1 // Datapath unit – structural model module Datapath_2_STR #(parameter dp_width = 8, R2_width = 4) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 334 ( output [R2_width -1: 0] count, output Zero, input [dp_width -1: 0] data, input Load_regs, Add_shift, clock, reset_b); supply1 pwr; supply0 gnd; wire [dp_width -1: 0] R1_Dbus, R1; wire [R2_width -1: 0] R2_Dbus; wire DR1_0, DR1_1, DR1_2, DR1_3, DR1_4, DR1_5, DR1_6, DR1_7; wire R1_0, R1_1, R1_2, R1_3, R1_4, R1_5, R1_6, R1_7; wire R2_0, R2_1, R2_2, R2_3; wire [R2_width -1: 0] R2 = {R2_3, R2_2, R2_1, R2_0}; assign count = {R2_3, R2_2, R2_1, R2_0}; assign R1 = { R1_7, R1_6, R1_5, R1_4, R1_3, R1_2, R1_1, R1_0}; assign DR1_0 = R1_Dbus[0]; assign DR1_1 = R1_Dbus[1]; assign DR1_2 = R1_Dbus[2]; assign DR1_3 = R1_Dbus[3]; assign DR1_4 = R1_Dbus[4]; assign DR1_5 = R1_Dbus[5]; assign DR1_6 = R1_Dbus[6]; assign DR1_7 = R1_Dbus[7]; nor (Zero, R1_0, R1_1, R1_2, R1_3, R1_4, R1_5, R1_6, R1_7); not (Load_regs_b, Load_regs); DFF DF_0 (R1_0, DR1_0, clock, pwr); DFF DF_1 (R1_1, DR1_1, clock, pwr); DFF DF_2 (R1_2, DR1_2, clock, pwr); DFF DF_3 (R1_3, DR1_3, clock, pwr); DFF DF_4 (R1_4, DR1_4, clock, pwr); DFF DF_5 (R1_5, DR1_5, clock, pwr); DFF DF_6 (R1_6, DR1_6, clock, pwr); DFF DF_7 (R1_7, DR1_7, clock, pwr); // Disable reset DFF DR_0 (R2_0, DR2_0, clock, Load_regs_b); // Load_regs (set) drives R2 to all ones DFF DR_1 (R2_1, DR2_1, clock, Load_regs_b); DFF DR_2 (R2_2, DR2_2, clock, Load_regs_b); DFF DR_3 (R2_3, DR2_3, clock, Load_regs_b); assign DR2_0 = R2_Dbus[0]; assign DR2_1 = R2_Dbus[1]; assign DR2_2 = R2_Dbus[2]; assign DR2_3 = R2_Dbus[3]; wire [1: 0] wire [dp_width -1: 0] wire [R2_width -1: 0] sel = {Add_shift, Load_regs}; R1_shifted = {1'b0, R1_7, R1_6, R1_5, R1_4, R1_3, R1_2, R1_1}; sum = R2 + {3'b000, R1[0]}; Mux8_4_x_1 M0 (R1_Dbus, R1, data, R1_shifted, R1, sel); Mux4_2_x_1 M1 (R2_Dbus, R2, sum, Add_shift); endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 335 module Mux8_4_x_1 #(parameter dp_width = 8) (output reg [dp_width -1: 0] mux_out, input [dp_width -1: 0] in0, in1, in2, in3, input [1: 0] sel); always @ (in0, in1, in2, in3, sel) case (sel) 2'b00: mux_out = in0; 2'b01: mux_out = in1; 2'b10: mux_out = in2; 2'b11: mux_out = in3; endcase endmodule module Mux4_2_x_1 #(parameter dp_width = 4) (output [dp_width -1: 0] mux_out, input [dp_width -1: 0] in0, in1, input sel); assign mux_out = sel ? in1: in0; endmodule // Test Plan for Datapath Unit: // Demonstrate action of Load_regs // R1 gets data, R2 gets all ones // Demonstrate action of Incr_R2 // Demonstrate action of Add_shift and detect Zero // Test bench for datapath module t_Datapath_Unit #(parameter dp_width = 8, R2_width = 4) ( ); wire [R2_width -1: 0] count; wire Zero; reg [dp_width -1: 0] data; reg Load_regs, Add_shift, clock, reset_b; Datapath_2_STR M0 (count, Zero, data, Load_regs, Add_shift, clock, reset_b); initial #250 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin reset_b = 0; #2 reset_b = 1; end initial fork data = 8'haa; Load_regs = 0; Add_shift = 0; #10 Load_regs = 1; #20 Load_regs = 0; #50 Add_shift = 1; #140 Add_shift = 0; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 336 Name 0 50 100 150 clock reset_b Load_regs Add_shift Zero aa data[7:0] R1[7:0] xx aa 55 2a 15 0a 05 02 01 00 R2[3:0] x 0 1 2 3 4 count[3:0] x 0 1 2 3 4 // Integrated system module Count_Ones_2_Gates_1Hot_STR # (parameter dp_width = 8, R2_width = 4) ( output [R2_width -1: 0] count, input [dp_width -1: 0] data, input Start, clock, reset_b ); wire Load_regs, Add_shift, Zero; Controller_2_Gates_1Hot M0 (Ready, Load_regs, Add_shift, Start, Zero, clock, reset_b); Datapath_2_STR M1 (count, Zero, data, Load_regs, Add_shift, clock, reset_b); endmodule // Test plan for integrated system // Test for data values of 8'haa, 8'h00, 8'hff. // Test bench for integrated system module t_Count_Ones_2_Gates_1Hot_STR (); parameter dp_width = 8, R2_width = 4; wire [R2_width -1: 0] count; reg [dp_width -1: 0] data; reg Start, clock, reset_b; wire [1: 0] state = {M0.M0.T1, M0.M0.T0}; Count_Ones_2_Gates_1Hot_STR M0 (count, data, Start, clock, reset_b); initial #700 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin reset_b = 0; #2 reset_b = 1; end initial fork data = 8'haa; // Expect count = 4 Start = 0; #20 Start = 1; #30 Start = 0; #40 data = 8'b00; // Expect count = 0 #120 Start = 1; #130 Start = 0; #150 data = 8'hff; // Expect count = 8 #200 Start = 1; #210 Start = 0; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 337 Name 0 80 160 240 1 2 320 400 clock reset_b Start Zero Load_regs Add_shift 1 state[1:0] 2 1 aa data[7:0] 2 1 00 ff R1[7:0] xx 00 ff 7f 3f 1f 0f R2[3:0] x 0 1 2 3 4 0 1 2 3 4 5 6 7 00 8 count[3:0] x 0 1 2 3 4 0 1 2 3 4 5 6 7 8 8.38 module Prob_8_38 ( output reg [7: 0] Sum, output reg Car_Bor, input [7: 0] Data_A, Data_B); reg [7: 0] Reg_A, Reg_B; always @ (Data_A, Data_B) case ({Data_A[7], Data_B[7]}) 2'b00, 2'b11: begin // ++, -{Car_Bor, Sum[6: 0]} = Data_A[6: 0] + Data_B[6: 0]; Sum[7] = Data_A[7]; end default: if (Data_A[6: 0] >= Data_B[6: 0]) begin // +-, -+ {Car_Bor, Sum[6: 0]} = Data_A[6: 0] - Data_B[6: 0]; Sum[7] = Data_A[7]; end else begin {Car_Bor, Sum[6: 0]} = Data_B[6: 0] - Data_A[6: 0]; Sum[7] = Data_B[7]; end endcase endmodule module t_Prob_8_38 (); wire [7: 0] Sum; wire Car_Bor; reg [7: 0] Data_A, Data_B; wire [6: 0] Mag_A, Mag_B; assign Mag_A = M0.Data_A[6: 0]; assign Mag_B = M0.Data_B[6: 0]; wire Sign_A = M0.Data_A[7]; wire Sign_B = M0.Data_B[7]; wire Sign = Sum[7]; wire [7: 0] Mag = Sum[6: 0]; // Hierarchical dereferencing Prob_8_38 M0 (Sum, Car_Bor, Data_A, Data_B); initial #650 $finish; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 338 initial fork // Addition // A B #0 begin Data_A = {1'b0, 7'd25}; Data_B = {1'b0, 7'd10}; end #40 begin Data_A = {1'b1, 7'd25}; Data_B = {1'b1, 7'd10}; end #80 begin Data_A = {1'b1, 7'd25}; Data_B = {1'b0, 7'd10}; end #120 begin Data_A = {1'b0, 7'd25}; Data_B = {1'b1, 7'd10}; end // B A #160 begin Data_B = {1'b0, 7'd25}; Data_A = {1'b0, 7'd10}; end #200 begin Data_B = {1'b1, 7'd25}; Data_A = {1'b1, 7'd10}; end //+25, +10 // -25, -10 // -25, +10 // 25, -10 //+25, +10 // -25, -10 #240 begin Data_B = {1'b1, 7'd25}; Data_A = {1'b0, 7'd10}; end #280 begin Data_B = {1'b0, 7'd25}; Data_A = {1'b1, 7'd10}; end // Addition of matching numbers // -25, +10 // +25, -10 #320 begin Data_A = {1'b1,7'd0}; Data_B = {1'b1,7'd0}; end #360 begin Data_A = {1'b0,7'd0}; Data_B = {1'b0,7'd0}; end #400 begin Data_A = {1'b0,7'd0}; Data_B = {1'b1,7'd0}; end #440 begin Data_A = {1'b1,7'd0}; Data_B = {1'b0,7'd0}; end // -0, -0 // +0, +0 // +0, -0 // -0, +0 #480 begin Data_B = {1'b0, 7'd25}; Data_A = {1'b0, 7'd25}; end #520 begin Data_B = {1'b1, 7'd25}; Data_A = {1'b1, 7'd25}; end // matching + // matching – // Test of carry (negative numbers) #560 begin Data_A = 8'hf0; Data_B = 8'hf0; end // Test of carry (positive numbers) #600 begin Data_A = 8'h70; Data_B = 8'h70; end join endmodule Name 0 // carry - // carry ++ 190 Data_A[7:0] 19 Data_B[7:0] 0a 99 8a 0a 19 0a 8a 19 380 8a 0a 99 8a 80 19 80 00 00 80 570 80 19 99 f0 70 00 19 99 f0 70 Sign_A Sign_B Mag_A[6:0] 25 10 0 25 112 Mag_B[6:0] 10 25 0 25 112 Car_Bor Sum[7:0] 23 a3 8f 0f 23 a3 8f 0f 80 00 80 32 b2 e0 60 Sign Mag[7:0] 35 15 35 15 0 50 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 96 8.39 339 Block diagram and ASMD chart: data_AR data_BR 16 zero 16 Datapath AR Ld_regs Controller ... Add_decr ... start BR ... done reset_b clock PR 16 PR reset_b s0 done AR <= data_A BR <= data_B PR <= 0 start 1 Ld_regs PR <= PR + BR AR <= AR -1 s1 Add_decr Zero 1 module Prob_8_39 ( output [15: 0] PR, output done, input [7: 0] data_AR, data_BR, input start, clock, reset_b ); Controller_P8_39 M0 (done, Ld_regs, Add_decr, start, zero, clock, reset_b); Datapath_P8_39 M1 (PR, zero, data_AR, data_BR, Ld_regs, Add_decr, clock, reset_b); endmodule module Controller_P8_16 (output done, output reg Ld_regs, Add_decr, input start, zero, clock, reset_b); parameter s0 = 1'b0, s1 = 1'b1; reg state, next_state; assign done = (state == s0); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 340 always @ (posedge clock, negedge reset_b) if (!reset_b) state <= s0; else state <= next_state; always @ (state, start, zero) begin Ld_regs = 0; Add_decr = 0; case (state) s0: if (start) begin Ld_regs = 1; next_state = s1; end s1: if (zero) next_state = s0; else begin next_state = s1; Add_decr = 1; end default: next_state = s0; endcase end endmodule module Datapath_P8_16 ( output reg [15: 0] PR, output zero, input [7: 0] data_AR, data_BR, input Ld_regs, Add_decr, clock, reset_b ); reg [7: 0] AR, BR; assign zero = ~( | AR); always @ (posedge clock, negedge reset_b) if (!reset_b) begin AR <= 8'b0; BR <= 8'b0; PR <= 16'b0; end else begin if (Ld_regs) begin AR <= data_AR; BR <= data_BR; PR <= 0; end else if (Add_decr) begin PR <= PR + BR; AR <= AR -1; end end endmodule // Test plan – Verify; // Power-up reset // Data is loaded correctly // Control signals assert correctly // Status signals assert correctly // start is ignored while multiplying // Multiplication is correct // Recovery from reset on-the-fly module t_Prob_P8_16; wire done; wire [15: 0] PR; reg [7: 0] data_AR, data_BR; reg start, clock, reset_b; Prob_8_16 M0 (PR, done, data_AR, data_BR, start, clock, reset_b); initial #500 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork reset_b = 0; #12 reset_b = 1; #40 reset_b = 0; #42 reset_b = 1; #90 reset_b = 1; #92 reset_b = 1; join Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 341 initial fork #20 start = 1; #30 start = 0; #40 start = 1; #50 start = 0; #120 start = 1; #120 start = 0; join initial fork data_AR = 8'd5; data_BR = 8'd20; // AR > 0 #80 data_AR = 8'd3; #80 data_BR = 8'd9; #100 data_AR = 8'd4; #100 data_BR = 8'd9; join endmodule Name 0 30 60 90 120 reset_b clock start Ld_regs Add_decr zero state data_AR[7:0] 5 data_BR[7:0] 20 AR[7:0] 0 BR[7:0] 0 5 20 4 0 3 4 9 5 4 3 2 0 1 0 20 done PR[15:0] 0 0 20 40 60 80 100 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 342 8.40 Data_in[7: 0] 8 Ready Got_Data Done_Product Start Run Send_Data Datapath Shift_in A Shift_regs Controller Add_regs B Decr_P Q Shift_out reset_b P C clock 8 Zero Q0 Note: Q0 = Q[0] Data_out[7: 0] Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 343 reset S_idle /Ready B[7: 0] <= Data_in … B[31: 24] <= Data_in Q[7: 0] <= Data_in … Q[31: 24] <= Data_in Start 1 Shift_in S_Ld_0...6 /Shift_in S_Ld__7 /Got_Data S_wait_1 Run 1 1 S_add / Decr_P Q0 Run The bytes of data will be read sequentially. Registers Q and B are organized to act as byte-wide parallel shift registers, taking 8 clock cycles to fill the pipe. The least significant byte of the multiplicand enters the most significant byte of Q and then moves through the bytes of Q to enter B, then proceed to occupy successive bytes of B until it occupies the least significant byte of B, and so forth until both B and Q are filled. Wait states are used to wait for Run and Send_Data. P <= P-1 1 {C, A} <= A + B Add_regs S_shift /Shift_regs Zero 1 S_product /Done_Product S_wait_2 Send_ Data Send_ Data 1 Shift_out 1 Shift_out S_Send_0...6 /Shift_out Data_out <= P[7: 0] … P[31: 24] Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 344 module Prob_8_40 ( output [7: 0] Data_out, output Ready, Got_Data, Done_Product, input [7: 0] Data_in, input Start, Run, Send_Data, clock, reset_b ); Controller M0 ( Ready, Shift_in, Got_Data, Done_Product, Decr_P, Add_regs, Shift_regs, Shift_out, Start, Run, Send_Data, Zero, Q0, clock, reset_b ); Datapath M1(Data_out, Q0, Zero, Data_in, Start, Shift_in, Decr_P, Add_regs, Shift_regs, Shift_out, clock ); endmodule module Controller ( output reg Ready, Shift_in, Got_Data, Done_Product, Decr_P, Add_regs, Shift_regs, Shift_out, input Start, Run, Send_Data, Zero, Q0, clock, reset_b ); parameter reg [4: 0] S_idle = 5'd20, S_Ld_0 = 5'd0, S_Ld_1 = 5'd1, S_Ld_2 = 5'd2, S_Ld_3 = 5'd3, S_Ld_4 = 5'd4, S_Ld_5 = 5'd5, S_Ld_6 = 5'd6, S_Ld_7 = 5'd7, S_wait_1 = 5'd8, // Wait state S_add = 5'd9, S_Shift = 5'd10, S_product = 5'd11, S_wait_2 = 5'd12, // Wait state S_Send_0 = 5'd13, S_Send_1 = 5'd14, S_Send_2 = 5'd15, S_Send_3 = 5'd16, S_Send_4 = 5'd17, S_Send_5 = 5'd18, S_Send_6 = 5'd19; state, next_state; always @ (posedge clock, negedge reset_b) if (~reset_b) state <= S_idle; else state <= next_state; always @ (state, Start, Run, Q0, Zero, Send_Data) begin next_state = S_idle; // Prevent accidental synthesis of latches Ready = 0; Shift_in = 0; Shift_regs = 0; Add_regs = 0; Decr_P = 0; Shift_out = 0; Got_Data = 0; Done_Product = 0; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 345 case (state) S_idle: S_Ld_0: S_Ld_1: S_Ld_2: S_Ld_3: S_Ld_4: S_Ld_5: S_Ld_6: S_Ld_7: S_wait_1: S_add: S_Shift: S_product: S_wait_2: S_Send_0: S_Send_1: S_Send_2: S_Send_3: S_Send_4: S_Send_5: S_Send_6: default: endcase end endmodule // Assign by exception to default values begin Ready = 1; if (Start) begin next_state = S_Ld_0; Shift_in = 1; end end begin next_state = S_Ld_1; Shift_in = 1; end begin next_state = S_Ld_2; Shift_in = 1; end begin next_state = S_Ld_3; Shift_in = 1; end begin next_state = S_Ld_4; Shift_in = 1; end begin next_state = S_Ld_5; Shift_in = 1; end begin next_state = S_Ld_6; Shift_in = 1; end begin next_state = S_Ld_7; Shift_in = 1; end begin Got_Data = 1; if (Run) next_state = S_add; else next_state = S_wait_1; end if (Run) next_state = S_add; else next_state = S_wait_1; begin next_state = S_Shift; Decr_P = 1; if (Q0) Add_regs = 1; end begin Shift_regs = 1; if (Zero) next_state = S_product; else next_state = S_add; end begin Done_Product = 1; if (Send_Data) begin next_state = S_Send_0; Shift_out = 1; end else next_state = S_wait_2; end if (Send_Data) begin next_state =S_Send_0; Shift_out = 1; end else next_state = S_wait_2; begin next_state = S_Send_1; Shift_out = 1; end begin next_state = S_Send_2; Shift_out = 1; end begin next_state = S_Send_3; Shift_out = 1; end begin next_state = S_Send_4; Shift_out = 1; end begin next_state = S_Send_5; Shift_out = 1; end begin next_state = S_Send_6; Shift_out = 1; end begin next_state = S_idle; Shift_out = 1; end next_state = S_idle; module Datapath #(parameter dp_width = 32, P_width = 6) ( output [7: 0] Data_out, output Q0, Zero, input [7: 0] Data_in, input Start, Shift_in, Decr_P, Add_regs, Shift_regs, Shift_out, clock ); reg [dp_width - 1: 0] A, B, Q; // Sized for datapath reg C; reg [P_width - 1: 0] P; assign Q0 = Q[0]; assign Zero = (P == 0); // counter is zero assign Data_out = {C, A, Q}; always @ (posedge clock) begin if (Shift_in) begin P <= dp_width; A <= 0; C <= 0; B[7: 0] <= B[15: 8]; // Treat B and Q registers as a pipeline to load data bytes B[15: 8] <= B[ 23: 16]; B[23: 16] <= B[31: 24]; B[31: 24] <= Q[7: 0]; Q[7: 0] <= Q[15: 8]; Q[15: 8] <= Q[ 23: 16]; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 346 Q[23: 16] <= Q[31: 24]; Q[31: 24] <= Data_in; end if (Add_regs) {C, A} <= A + B; if (Shift_regs) {C, A, Q} <= {C, A, Q} >> 1; if (Decr_P) P <= P -1; if (Shift_out) begin {C, A, Q} <= {C, A, Q} >> 8; end end endmodule module t_Prob_8_40; parameter dp_width = 32; // Width of datapath wire [7: 0] Data_out; wire Ready, Got_Data, Done_Product; reg Start, Run, Send_Data, clock, reset_b; integer Exp_Value; reg Error; wire [7: 0] Data_in; reg [dp_width -1: 0] Multiplicand, Multiplier; reg [2*dp_width -1: 0] Data_register; // For test patterns assign Data_in = Data_register [7:0]; wire [2*dp_width -1: 0] product; assign product = {M0.M1.C, M0.M1.A, M0.M1.Q}; Prob_8_40 M0 ( Data_out, Ready, Got_Data, Done_Product, Data_in, Start, Run, Send_Data, clock, reset_b ); initial #2000 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork reset_b = 1; #2 reset_b = 0; #3 reset_b = 1; join initial fork Start =0; Run = 0; Send_Data = 0; #10 Start = 1; #20 Start = 0; #50 Run= 1; #60 Run = 0; #120 Run = 1; #130 Run = 0; // Ignored by controller #830 Send_Data = 1; #840 Send_Data = 0; join // Test patterns for multiplication initial begin Multiplicand = 32'h0f_00_00_aa; Multiplier = 32'h0a_00_00_ff; Data_register = {Multiplier, Multiplicand}; end initial begin // Synchronize input data bytes @ (posedge Start) repeat (15) begin Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 347 @ (negedge clock) Data_register <= Data_register >> 8; end end endmodule Simulation results: Loading multiplicand (0f0000aaH) and multiplier (0a0000ffH), 4 bytes each, in sequence, beginning with the least significant byte of the multiplicand. Note: Product is not valid until Done_Product asserts. The value of Product shown here (25510) reflects the contents of {C, A, Q} after the multiplier has been loaded, prior to multiplication. Note: The machine ignores a premature assertion of Run. Note: Got_Data asserts at the 8th clock after Start asserts, i.e., 8 clocks to load the data. Note: Product, Multiplier, and Multiplicand are formed in the test bench. Launch activity at rising edge of clock Name Ignore Run Loading 8 bytes of data 0 Respond to Run Waiting for Run 40 80 120 160 clock reset_b Start Run Send_Data Zero Q0 Ready Got_Data Done_Product Shift_in Shift_regs Add_regs Decr_P Shift_out state[4:0] 20 Data_in[7:0] 170 P[31:0] x 0 1 2 0 3 15 4 5 255 6 0 7 8 9 10 9 10 0 32 31 xxxxxxxx B[31:0] 10 30 0f0000aa C 00000000 A[31:0] 0a0000ff Q[31:0] Multiplicand[31:0] 0f0000aa Multiplicand[31:0] 251658410 Multiplier[31:0] 0a0000ff Multiplier[31:0] 167772415 000000000a0000ff product[63:0] product[63:0] Data_out[7:0] x x x x X 167772415 170 0 15 255 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 127 348 Note: Product (64 bits) is formed correctly Multiplication complete Name 735 Begin sending data bytes of product. Waiting for Send_Data 785 835 885 935 clock reset_b Start Run Send_Data Zero Q0 Ready Got_Data Done_Product Shift_in Shift_regs Add_regs Decr_P Shift_out state[4:0] 10 9 10 11 12 13 14 15 16 17 18 19 20 0 Data_in[7:0] 1 P[31:0] 0 0f0000aa B[31:0] C A[31:0] 00960015 Q[31:0] 9500a956 00000000 00000000 Multiplicand[31:0] 0f0000aa Multiplicand[31:0] 251658410 Multiplier[31:0] 0a0000ff Multiplier[31:0] 167772415 product[63:0] 009600159500a956 product[63:0] 42221339200760150 Data_out[7:0] 88 172 86 0 0 21 0 0 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 349 Multiplication complete Name 735 Begin sending data bytes of product. Waiting for Send_Data 785 Data sent - {C, A, Q} empty. State = S_idle 835 885 935 clock reset_b Start Run Send_Data Zero Q0 Ready Got_Data Done_Product Shift_in Shift_regs Add_regs Decr_P Shift_out state[4:0] 10 9 10 11 12 13 14 15 16 17 18 19 20 0 Data_in[7:0] 1 P[31:0] 0 0f0000aa B[31:0] C A[31:0] 00960015 Q[31:0] 9500a956 00000000 00000000 Multiplicand[31:0] 0f0000aa Multiplicand[31:0] 251658410 Multiplier[31:0] 0a0000ff Multiplier[31:0] 167772415 product[63:0] 009600159500a956 product[63:0] 42221339200760150 Data_out[7:0] 88 172 86 0 0 21 0 0 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 8.41 350 (a) Data 8 P1[7: 0] P0[7: 0] 8 P1[7: 0] P0[7: 0] 8 R0[15: 0] {P1, P0} <= {0, 0} S_idle rst 1 Clr_P1_P0 1 En Ld_P1_P0 P1 <= Data P0 <= P1 {P1, P0} <= {0, 0} 1 P1 <= Data S_1 P0 <= P1 Ld_P1_P0 Clr_P1_P0 S_full ld_P1_P0 S_wait Ld 1 Ld 1 1 Ld_R0 P1 <= Data P0 <= P1 En R0 <= {P1, P0} (b) HDL model, test bench and simulation results for datapath unit. module Datapath_unit ( output reg [15: 0] R0, input [7: 0] Data, input Clr_P1_P0, Ld_P1_P0, Ld_R0, clock, rst); reg [7: 0] P1, P0; always @ (posedge clock) begin if (Clr_P1_P0) begin P1 <= 0; P0 <= 0; end if (Ld_P1_P0) begin P1 <= Data; P0 <= P1; end if (Ld_R0) R0 <= {P1, P0}; end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 351 // Test bench for datapath module t_Datapath_unit (); wire [15: 0] R0; reg [7: 0] Data; reg Clr_P1_P0, Ld_P1_P0, Ld_R0, clock, rst; Datapath_unit M0 (R0, Data, Clr_P1_P0, Ld_P1_P0, Ld_R0, clock, rst); initial #100 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin rst = 0; #2 rst = 1; end initial fork #20 Clr_P1_P0 = 0; #20 Ld_P1_P0 = 0; #20 Ld_R0 = 0; #20 Data = 8'ha5; #40 Ld_P1_P0 = 1; #50 Data = 8'hff; #60 Ld_P1_P0 = 0; #70 Ld_R0 = 1; #80 Ld_R0 = 0; join endmodule Name 0 50 100 clock rst Clr_P1_P0 Ld_P1_P0 Ld_R0 Data[7:0] P1[7:0] P0[7:0] R0[15:0] xx a5 xx ff a5 xx ff a5 xxxx ffa5 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 352 (c) HDL model, test bench, and simulation results for the control unit. module Control_unit (output reg Clr_P1_P0, Ld_P1_P0, Ld_R0, input En, Ld, clock, rst); parameter S_idle = 4'b0001, S_1 = 4'b0010, S_full = 4'b0100, S_wait = 4'b1000; reg [3: 0] state, next_state; always @ (posedge clock) if (rst) state <= S_idle; else state <= next_state; always @ (state, Ld, En) begin Clr_P1_P0 = 0; // Assign by exception Ld_P1_P0 = 0; Ld_R0 = 0; next_state = S_idle; case (state) S_idle: if (En) begin Ld_P1_P0 = 1; next_state = S_1; end else next_state = S_idle; S_1: begin Ld_P1_P0 = 1; next_state = S_full; end S_full: if (!Ld) next_state = S_wait; else begin Ld_R0 = 1; if (En) begin Ld_P1_P0 = 1; next_state = S_1; end else begin Clr_P1_P0 = 1; next_state = S_idle; end end S_wait: if (!Ld) next_state = S_wait; else begin Ld_R0 = 1; if (En) begin Ld_P1_P0 = 1; next_state = S_1; end else begin Clr_P1_P0 = 1; next_state = S_idle; end end next_state = S_idle; default: endcase end endmodule // Test bench for control unit module t_Control_unit (); wire Clr_P1_P0, Ld_P1_P0, Ld_R0; reg En, Ld, clock, rst; Control_unit M0 (Clr_P1_P0, Ld_P1_P0, Ld_R0, En, Ld, clock, rst); initial #200 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin rst = 0; #2 rst = 1; #12 rst = 0; end initial fork #20 Ld = 0; #20 En = 0; #30 En = 1; // Drive to S_wait #70 Ld = 1; // Return to S_1 to S_full tp S_wait #80 Ld = 0; #100 Ld = 1; // Drive to S_idle #100 En = 0; #110 En = 0; #120 Ld = 0; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 353 Name 0 50 100 150 clock rst En Ld Clr_P1_P0 Ld_P1_P0 Ld_R0 state[3:0] x 1 2 4 8 2 4 8 1 (c) Integrated system Note that the test bench for the integrated system uses the input stimuli from the test bench for the control unit and displays the waveforms produced by the test bench for the datapath unit.: module Prob_8_41 (output [15: 0] R0, input [7: 0] Data, input En, Ld, clock, rst); wire Clr_P1_P0, Ld_P1_P0, Ld_R0; Control_unit M0 (Clr_P1_P0, Ld_P1_P0, Ld_R0, En, Ld, clock, rst); Datapath_unit M1 (R0, Data, Clr_P1_P0, Ld_P1_P0, Ld_R0, clock); endmodule module Control_unit (output reg Clr_P1_P0, Ld_P1_P0, Ld_R0, input En, Ld, clock, rst); parameter S_idle = 4'b0001, S_1 = 4'b0010, S_full = 4'b0100, S_wait = 4'b1000; reg [3: 0] state, next_state; always @ (posedge clock) if (rst) state <= S_idle; else state <= next_state; always @ (state, Ld, En) begin Clr_P1_P0 = 0; // Assign by exception Ld_P1_P0 = 0; Ld_R0 = 0; next_state = S_idle; case (state) S_idle: if (En) begin Ld_P1_P0 = 1; next_state = S_1; end else next_state = S_idle; S_1: begin Ld_P1_P0 = 1; next_state = S_full; end S_full: if (!Ld) next_state = S_wait; else begin Ld_R0 = 1; if (En) begin Ld_P1_P0 = 1; next_state = S_1; end else begin Clr_P1_P0 = 1; next_state = S_idle; end end S_wait: if (!Ld) next_state = S_wait; else begin Ld_R0 = 1; if (En) begin Ld_P1_P0 = 1; next_state = S_1; end Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 354 else begin Clr_P1_P0 = 1; next_state = S_idle; end end next_state = S_idle; default: endcase end endmodule module Datapath_unit ( output reg [15: 0] R0, input [7: 0] Data, input Clr_P1_P0, Ld_P1_P0, Ld_R0, clock); reg [7: 0] P1, P0; always @ (posedge clock) begin if (Clr_P1_P0) begin P1 <= 0; P0 <= 0; end if (Ld_P1_P0) begin P1 <= Data; P0 <= P1; end if (Ld_R0) R0 <= {P1, P0}; end endmodule // Test bench for integrated system module t_Prob_8_41 (); wire [15: 0] R0; reg [7: 0] Data; reg En, Ld, clock, rst; Prob_8_41 M0 (R0, Data, En, Ld, clock, rst); initial #200 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial begin rst = 0; #10 rst = 1; #20 rst = 0; end initial fork #20 Data = 8'ha5; #50 Data = 8'hff; #20 Ld = 0; #20 En = 0; #30 En = 1; // Drive to S_wait #70 Ld = 1; // Return to S_1 to S_full tp S_wait #80 Ld = 0; #100 Ld = 1; // Drive to S_idle #100 En = 0; #110 En = 0; #120 Ld = 0; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 355 Name 0 40 80 120 clock rst En Ld Clr_P1_P0 Ld_P1_P0 Ld_R0 state[3:0] Data[7:0] P1[7:0] P0[7:0] R0[15:0] x 1 xx 2 4 8 a5 xx 4 ff a5 xxxx 8 1 ff a5 xx 2 00 ff a5a5 00 ffff Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 356 8.42 module Datapath_BEH #(parameter dp_width = 8, R2_width = 4) ( output [R2_width -1: 0] count, output E, //output reg E, output Zero, input [dp_width -1: 0] data, input Load_regs, Shift_left, Incr_R2, clock, reset_b); reg [dp_width -1: 0] R1; reg [R2_width -1: 0] R2; assign E = R1[dp_width -1]; assign count = R2; assign Zero = ~(| R1); always @ (posedge clock) begin // E <= R1[dp_width -1] & Shift_left; // if (Load_regs) begin R1 <= data; R2 <= {R2_width{1'b1}}; end if (Load_regs) begin R1 <= data; R2 <= {R2_width{1'b0}}; end if (Shift_left) R1 <= R1 << 1; //if (Shift_left) {E, R1} <= {E, R1} << 1; if (Incr_R2) R2 <= R2 + 1; end endmodule module Controller_BEH ( output Ready, output reg Load_regs, output Incr_R2, Shift_left, input Start, Zero, E, clock, reset_b ); parameter S_idle = 0, S_1 = 1, S_2 = 2, S_3 = 3; reg [1:0] state, next_state; assign Ready = (state == S_idle); assign Incr_R2 = (state == S_1); assign Shift_left = (state == S_2); always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= S_idle; else state <= next_state; always @ (state, Start, Zero, E) begin Load_regs = 0; case (state) S_idle: if (Start) begin Load_regs = 1; next_state = S_1; end else next_state = S_idle; S_1: if (Zero) next_state = S_idle; else next_state = S_2; S_2: //S_3: S_3: next_state = S_3; if (E) next_state = S_1; else next_state = S_2; if (E) next_state = S_1; else if (Zero) next_state = S_idle; else next_state = S_2; endcase end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. // Integrated system module Count_Ones_BEH_BEH # (parameter dp_width = 8, R2_width = 4) ( output [R2_width -1: 0] count, input [dp_width -1: 0] data, input Start, clock, reset_b ); wire Load_regs, Incr_R2, Shift_left, Zero, E; Controller_BEH M0 (Ready, Load_regs, Incr_R2, Shift_left, Start, Zero, E, clock, reset_b); Datapath_BEH M1 (count, E, Zero, data, Load_regs, Shift_left, Incr_R2, clock, reset_b); endmodule // Test plan for integrated system // Test for data values of 8'haa, 8'h00, 8'hff. // Test bench for integrated system module t_count_Ones_BEH_BEH (); parameter dp_width = 8, R2_width = 4; wire [R2_width -1: 0] count; reg [dp_width -1: 0] data; reg Start, clock, reset_b; Count_Ones_BEH_BEH M0 (count, data, Start, clock, reset_b); initial #700 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial bebgin reset_b = 0; #2 reset_b = 1; enbd initial fork data = 8'haa; // Expect count = 4 Start = 0; #20 Start = 1; #30 Start = 0; #40 data = 8'b00; // Expect count = 0 #250 Start = 1; #260 Start = 0; #280 data = 8'hff; #280 Start = 1; #290 Start = 0; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 357 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 358 359 CHAPTER 9 9.1 Oscilloscope display: clock 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 QB 0 QC 0 QD 0 BCD count: Oscilloscope displays from 0000 to 1001 Output pattern: QA = alternate 1's and 0s QB = Two 1's, two 0's, two 1's, four 0's QC = Four 1's, six 0's QD = Two 1's, eight 0's. Other counts: (a) 0101 must reset at 0110 – connect QB to R1, QC to R2 (b) 0111 must reset at 1000 – connect QD to both R1 and R2 (c) 1011 must reset at 1100 – connect QC to R1, QD to R2 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 9.2 360 Truth table: Inputs A 0 0 1 1 B 0 1 0 1 NAND 1 1 1 0 NOR NOT(A) 0 1 1 0 1 1 1 0 AND 0 0 0 1 OR XOR 0 0 1 1 1 1 1 0 Waveforms: QA 0 1 0 1 0 0 1 1 1 1 1 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 0 QB NAND(7400) NOR(7492) NOT( A (7404) AND (7408) OR (7432) xOR (7486) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 361 9.3 Logic Diagram x y yz 00 0 x 01 m0 m4 1 11 m1 m5 1 m3 m7 1 F = xy' + yz x 10 m2 1 m6 1 F y z 7400 z Boolean Functions: AB Boolean Functions: CD C 00 00 01 11 A 10 m0 m4 1 1 01 m1 m5 11 1 1 m3 m2 m7 m6 m15 m14 m8 m9 m11 m10 1 1 B 11 A 1 10 D F1 = C' + AB'D' C 00 01 m13 1 CD 00 m12 1 AB 10 01 11 m1 m3 m4 m5 m7 m12 m13 m15 m14 m8 m9 m11 m10 1 1 1 1 1 1 1 m2 m6 B 1 D F2 = BD + CD + AB'D' 2 ICs: 7400, 7410 C B 10 m0 F1 A D F2 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 362 Complement: AB CD C 00 00 01 11 A 10 m0 m4 01 m1 0 m5 0 11 m3 1 m7 1 10 D 1 B m2 1 m6 1 m13 m15 m14 m8 m9 m11 m10 0 1 0 1 1 C 0 m12 F B 0 1 F' 1 2 - 7400 ICs D F = D + B'C F' = C'D' + BD' 9.4 Design Example: AB CD C 00 00 01 11 A 10 m0 01 11 m1 10 m3 F = AB' + BC + BD m2 A m4 m5 m12 m13 m15 m14 m8 m9 m11 m10 1 m7 1 1 m6 1 1 1 1 1 1 B B C F D 1/3 7410 1 7400 D Majority Logic x 00 0 x 1 F = xy + xz + yz y yz 01 11 m0 m1 m3 m4 m5 m7 1 1 1 10 m2 m6 x y F z 1 1/3 7410 7400 z A B Peven Podd C D VCC x 1 = x' Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 363 Decoder Implementation 1 F1 = xz + x'y'z' = Σ (0, 5, 7) x y z F2 = x'y+ xy'z' = Σ (2, 3, 4) F3 = xy+ x'y'z = Σ (1, 6, 7) 15 C1 C2 B A G1 74155 G2 9 10 11 12 7 6 5 4 0 1 2 3 4 5 6 7 9 6 4 F1 11 12 7 F2 10 5 4 F3 7410 8 9.5 Gray code to Binary – See solution to Prob. 4.7. 9's complementer – See solution to Prob. 4.18. w = A'B'C' x = BC' + B'C y=C z = D' E = AB + AC 3 ICs: 7400, 7404, 7410 A A' B B' C C' w B C' x B' C D y z A B E A C Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 364 9.6 Four 7451's See implementation tables below w 8 Mux A A 8 Mux B B 8 Mux C C 8 Mux D D C B A 7447 7730 Fig. 11.8 x y z A = ∑ (0, 2, 3, 6, 7, 8, 9, 12, 13) B = ∑ (0, 2, 3, 4, 512, 13, 14) C = ∑ (0, 1, 3, 5, 6, 9, 10, 13, 14) D = ∑ (0, 7, 11) Mux B D0 D1 D2 Mux A D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 1 w w' w' w w w' w' w' 0 w' w' 1 1 w 0 D0 D1 D2 Mux C D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 w' 1 w w' 1 1 0 w' 0 0 w 0 0 0 w' 0 Mux D 9.7 Half - Adder x y S C Full- Adder x y S C z Parallel adder - See circuit of Fig. 9.10. Adder-subtractor – See circuit of Fig. 9.11. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 365 Operation 9 + 5 = 14 9 + 9 = 19 = 16 + 2 9 + 15 = 24 = 16 + 8 9-5=4 9-9=0 9 - 15 = -6 A 4 B 4 Inputs A B C0 S 0 0 0 1 1 1 1001 1001 1001 1001 1001 1001 0 0 0 1 1 1 1110 0010 1000 0100 0000 1010 0101 1001 1111 0101 1001 1111 Outputs C4 0 1 1 1 1 0 sum < 15 sum > 15 sum > 15 A>B A=B AB y A=B x S1 M=1 9.8 M SR Latch: See Fig. 5.4. D Latch: D Q Let CP = C, x = output of gate 4. x = [(DC)'C]' = (D'C)' C 4 Q' x Master-Slave D Flip-Flop: The circuit is as in Fig. 5.9. The oscilloscope display: Clock Master Y Slave Q Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 366 Edge-Triggered D Flip-Flop: Circuit is shown in Fig. 5.10. Clock Output IC Flip-Flops: Connect all inputs to toggle switches, the clock to a pulser, and the outputs to indicator lamps. 9.9 Up-Down Counter with Enable: B A 7476 Q1 Q Q1 Q K J K J clock E x 7410 JB = KB = E (Complement B when E = 1) JA = KA = E (Bx + B'x') Complement A when E = 1 and: B = 1 when x = 1 (Count up) B = 0 when x = 0 (Count down) State Diagram: JA = B KA = B' JB = Ax + A'x' = (A ⊕ x)' KB = Ax + A'x' = (A ⊕ x)' Y=A⊕B⊕x A x (A x)' = JB = KB Logic 1 y B Design of Counter: ABCD JA = KA = B(CD) JB = KB = CD JC = D JD = K D = 1 0000 → 0101 → 090 1000 → 1001 → 1010 KC = AD Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 9.10 367 Ripple counter: See Fig. 6.8 Down counter: Either take outputs from Q' outputs or connect complement Q' to next clock input. Synchronous counter: See Fig. 6.12. BCD counter: See solution to Prob. 6.19. Unused states: 10 11 6 12 13 4 14 15 2 Binary counter wth parallel load: Connect QA and QD through a NAND gate to the load. See Fig. 6.15. 9.11 Ring counter: See Fig. 6.17(a). States of register: QA QB QC QD 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 Switch-tail ring counter: See Fig. 6.18(a). Connect (QD)' at pin 12 to the serial input at pin 4. State sequence as in Fig. 6.18(b). Feedback shift register: Serial input = QC ⊕ QD (Use 7486). Sequence of states: QA QB QC QD 1 0 0 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 368 Bidirectional shift register with parallel load: Function table: 74195 Clear Clock 0 1 1 1 1 74157 SH/LD x STROBE SELECT x 1 0 0 0 * x x 0 0 1 x x 1 0 x Function Async clear Shift right (QA QB) Shift left (Select B)* Parallel Load (Select A) Synchronous clear B inputs come from QA-QD shifted by one position. 9.12 To serial input of 74197 QD x 74197 (QD)' x' J y QD 74197 (QD)' Q K y' M = 0 for add, 1 for subtract 9.13 Testing the RAM: To 4 switches From pulser A QA D1 D2 D3 D4 A B QB B QC C QD WE D S1 S2 S3 S4 R1 7493 R2 GND vcc 7447 7730 Fig. 11.8 VCC GND Read ME To pulser Write 7404 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 369 Memory Expansion: Input address A B C D ME 7489 Input data D1 D2 D3 D4 Output data to indicator lamps WE A B C D ME 7489 Read D1 D2 D3 D4 WE Pulser Write 9.14 Circuit Analysis – Answers to questions: 1) Resets to 0 the two 74194 ICs, the two D flip-flops, and the start SR latch. This makes S1S0 = 11 (parallel load). 2) The start switch sets the SR latch to 1. The clock pulses load 0000_0001 into the 8-bit register. If the start switch stays on, the register never clears to all 0s when S1S0 = 11 (right-most QD stays on). 3) Pressing the pulser makes S1S0 = 10 and the light shifts left. When QC becomes 1, the start SR latch is cleared to 0. When QA of the left 74194 becomes 1, it changes S1 to 0 (through the PR input) and S0 to 1 (through the CLR input. with S1S0 = 01, the single light shifts right. 4) If the pulser is pressed while the light is moving to the left or the right, S1S0 becomes 11 and all 0s are loaded into the register in parallel. The light goes off. 5) When the right-most QD becomes a 1, S1S0 changes from 01 (shift right) to 11 (parallel load). If the pulser is pressed before the next clock pulse, S1S0 goes to 10 (shift left). If not pressed, an all 0s value is loaded into the register in parallel. (Provided the start switch is in the logic 1 position.) Lamp Ping-Pong Add a left pulser. Three wire changes to the D flip-flop on the left: 1) Connect the clock input of the flip-flop to the pulser. 2) Connect the D input to the QA of the left 74197 3) Connect the input of the inverter (that goes to PR) to ground. Counting the Losses QD Right-most flip-flop of shift register A 7493 Fig. 11.8 Fig. 11.4 S1 S0 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 9.15 370 Clock Pulse Generator tL = 0.693 RBC = 10-6 RB = 10-6 /(0.693 x 0.001 x 10-6) = 103 / 0.693 = 1.44 KΩ (Use RB = 1.5 KΩ) tH/tL = 0.693 (RA + RB)C /(0.693 RB C) = (RA + RB) / RB = 9/ 1 = 9 9 RB = RA + RB RA = 8 RB = 8 x 1.5 KΩ = 12 KΩ Oscilloscope Waveforms (Actual results may be off by + 20 %.) 5V Pin 3 output 0V 1 µs 9 µs Pin 2 or 6 across C 3.3 V = 0.66 VCC 1.1 V = 0.22 VCC 3.3 V 1.7 V Pin 7 Collector 0V Variable Frequency Pulse Generator: 20 KHz: 10-3 / 20 = 0.05 x 10-3 = 50 µs 100 KHz: 10-3 / 100 = 10-5 = 10 µs tH = 49 µs: (RA + RP + RB) / RB = 49/ 1 = 49 RP = 48 RB – RA = 48 x 1.5 – 11 = 60 KΩ 9.16 Control of Register 7476 Cout J Q Carry CP K QB 74194 SW1 S1 SW2 S2 SW1 0 0 1 SW2 0 No change 1 shift right 1 Load Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 371 Checking the Circuit: Initial + 0110 + 1110 + 1101 + 0101 + 0011 Carry 0 0 1 1 0 0 Register 0000 0110 0100 0001 0110 1001 Circuit Operation: Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 9.17 Carry RAM 0 0110 0 0110 0 0011 1110 1 0001 1 1000 1101 1 0101 1 1010 0101 0 1111 0 0111 0011 0 1010 0 0101 RAM Value RAM + Register Shfit Register RAM Value RAM + Register SHIFT RAM Value RAM + Register SHIFT RAM Value RAM + Register SHIFT RAM Value RAM + REgiser SHIFT Multiplication Example (11 x 15 = 165) Multiplicand B = 1111 C Initial: T2 = 1 T1= 1 Add B; P <= P+1 T3 = 1 T2 = 1 Shift CAQ Add B; P <= P+1 T3 = 1 T2 = 1 Shift CAQ P <= P+1 T3 = 1 T2 = 1 Shift CAQ Add B; P <= P+1 T3 = 1 Shift CAQ T0 = 1 (Because PC = 1) A 0 0000 1111 0 1111 0 0111 1111 1 0110 0 1011 0 1011 Q P 1011 0000 1011 0001 1101 0001 1101 0010 0110 0010 0110 0011 0 0101 1011 0011 1111 1 0100 1011 0100 0 1010 0101 0100 1010 0101 = Product Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 372 Data Processor Design Load Q Load A Shift AQ T1 T2Q1 T3 0 1 0 0 0 0 1 0 Register Q S1 S0 0 0 0 1 0 1 0 0 S1(Q) = T1 S4(Q) = T1 + T3 0 1 0 1 Register A S1 S0 0 0 1 0 0 0 1 1 S1(A) = T2Q1 S0(A) = T2Q1 + T3 T1 S1 T2 S0 of Q Q1 S1 of A S0 T3 7474 74161 Asynchronous clear P, A, and E P T D Cout E CP Design of Control: See Section 8.8. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 373 SOLUTIONS FOR SECTION 9.19 Supplement to Experiment 2: (a) w3 x w1 F=x y w2 y w4 Initially, with xy = 00, w1 = w2 = 1, w3 = w4 = 0 and F = 0. w1 should change to 0 10ns after xy changes to 01. w4 should change to 1 20 ns after xy changes to 01. F should change from 0 to 1 30 ns after w4 changes from 0 to 1, i.e., 50 ns after xy changes from 00 to 01. w3 should remain unchanged because x = 0 for the entire simulation. (b) `timescale 1ns/1ps module Prob_3_33 (output F, input x, y); wire w1, w2, w3, w4; and #20 (w3, x, w1); not #10 (w1, x); and #20 (w4, y, w1); not #10 (w2, y); or #30 (F, w3, w4); A endmodule module t_Prob_3_33 (); reg x, y; wire F; Prob_3_33 M0 (F, x, y); initial #200 $finish; initial fork x = 0; y = 0; #100 y = 1; join endmodule (c) To simulate the circuit, it is assumed that the inputs xy = 00 have been applied sufficiently long for the circuit to be stable before xy = 01 is applied. The testbench sets xy = 00 at t = 0 ns, and xy = 1 at t = 100 ns. The simulator assumes that xy = 00 has been applied long enough for the circuit to be in a stable state at t = 0 ns, and shows F = 0 as the value of the output at t = 0. The waveforms show the response to xy = 01 applied at t = 100 ns. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 374 Name 0.000ns 66.670ns 133.340ns 200.010ns x y w1 w2 w3 w4 F Δ = 50 ns Supplement to Experiment 4: (a) // Gate-level description of circuit in Fig. 4-2 module Circuit_of_Fig_4_2 ( output F1, F2, input A, B, C); wire T1, T2, T3, F2_not, E1, E2, E3; or G1 (T1, A, B, C); and G2 (T2, A, B, C); and G3 (E1, A, B); and G4 (E2, A, C); and G5 (E3, B, C); or G6 (F2, E1, E2, E3); not G7 (F2_not, F2); and G8 (T3, T1, F2_not); or G9 (F1, T2, T3); endmodule module t_Circuit_of_Fig_4_2; reg [2: 0] D; wire F1, F2; parameter stop_time = 100; Circuit_of_Fig_4_2 M1 (F1, F2, D[2], D[1], D[0]); initial # stop_time $finish; initial begin // Stimulus generator D = 3'b000; repeat (7) #10 D = D + 1'b1; end initial begin $display ("A B C $monitor ("%b %b end endmodule F1 F2"); %b %b %b", D[2], D[1], D[0], F1, F2); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 375 /* A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F1 0 1 1 0 1 0 0 1 F2 0 0 0 1 0 1 1 1 */ The simulation results demonstrate the behavior of a full adder, with F1 = sum, and F2 – carry. Name 0 60 A B C F1 F2 (b) // 3-INPUT MAJORITY DETECTOR CIRCUIT. // Circuit implements F = xy + xz +yz. module Majority_Detector (output F, input x, y, z); wire wl, w2, w3; nand nl(wl, x, y), n2(w2, x, z), n3(w3, y, z), n4(F, wl, w2, w3) ; endmodule // Test bench //Treating inputs to majority detector as a vector, reg [2:0]D; //D[2] = x, D[l] = y, D[0] = z. wire F; module t_Majority_Detector (); wire F; reg [2: 0] D; wire x = D[2]; wire y = D[1]; wire z = D[0]; Majority_Detector M0 (F, x, y, z); initial #100 $finish; initial $monitor ($time,, "xyz = %b F = %b", D, F); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 376 initial begin D = 0; repeat (7) #10 D = D + 1; end endmodule Simulation results: 0 xyz = 000 F = 0 10 xyz = 001 F = 0 20 xyz = 010 F = 0 30 xyz = 011 F = 1 40 xyz = 100 F = 0 50 xyz = 101 F = 1 60 xyz = 110 F = 1 70 xyz = 111 F = 1 Name 0 60 x y z F Supplement to Experiment 5: See the solution to Prob. 4.42. Supplement to Experiment 7: (a) //BEHAVIORAL DESCRIPTION OF 7483 4-BIT ADDER, module Adder_7483 ( output S4, S3, S2, S1, C4, input A4, A3, A2, A1, B4, B3, B2, B1, C0, VCC, GND ); // Note: connect VCC and GND to supply1 and supply0 in the test bench wire [4: 1] sum; wire [4: 1] A = {A4, A3, A2, A1}; wire [4: 1] B = {B4, B3, B2, B1}; assign S4 = sum[4]; assign S3 = sum[3]; assign S2 = sum[2]; assign S1 = sum[1]; assign {C4, sum} = A + B + C0; endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 377 module t_Adder_7483 (); wire S4, S3, S2, S1, C4; wire A4, A3, A2, A1, B4, B3, B2, B1; reg C0; supply1 VCC; supply0 GND; reg [4:1] A, B; assign A4 = A[4]; assign A3 = A[3]; assign A2 = A[2]; assign A1 = A[1]; assign B4 = B[4]; assign B3 = B[3]; assign B2 = B[2]; assign B1 = B[1]; Adder_7483 M0 (S4, S3, S2, S1, C4, A4, A3, A2, A1, B4, B3, B2, B1, C0, VCC, GND); initial #2600 $finish; initial begin A = 0; B = 0; C0 = 0; repeat (256) #5 {A, B} = {A, B} + 1; A = 0; B = 0; C0 = 1; repeat (256) #5 {A, B} = {A, B} + 1; end endmodule (b) module Supp_9_17b (output [4: 1] S, output carry, input [4: 1] A, B, input M, VCC, GND); wire B4, B3, B2, B1; xor (B4, M, B[4]); xor (B3, M, B[3]); xor (B2, M, B[2]); xor (B1, M, B[1]); Adder_7483 M0 (S[4], S[3], S[2], S[1], carry, A[4], A[3], A[2], A[1], B4, B3, B2, B1, M, VCC, GND); endmodule module Adder_7483 ( output S4, S3, S2, S1, C4, input A4, A3, A2, A1, B4, B3, B2, B1, C0, VCC, GND ); // Note: connect VCC and GND to supply1 and supply0 in the test bench wire [4: 1] sum; wire [4: 1] A = {A4, A3, A2, A1}; wire [4: 1] B = {B4, B3, B2, B1}; assign S4 = sum[4]; assign S3 = sum[3]; assign S2 = sum[2]; assign S1 = sum[1]; assign {C4, sum} = A + B + C0; endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 378 module t_Supp_9_17b (); wire [4: 1] S; wire carry; reg C0; reg [4: 1] A, B; reg M; supply1 VCC; supply0 GND; Supp_9_17b M0 (S, carry, A, B, M, VCC, GND); initial #2600 $finish; initial begin A = 0; B = 0; M = 0; repeat (256) #5 {A, B} = {A, B} + 1; A = 0; B = 0; M = 1; repeat (256) #5 {A, B} = {A, B} + 1; end endmodule (c), (d) module supp_9_7c (output S3, S2, S1, S0, C, V, input A3, A2, A1, A0, B3, B2, B1, B0, M); wire [3: 0] Sum, B; assign S3 = Sum[3]; assign S2 = Sum[2]; assign S1 = Sum[1]; assign S0 = Sum[0]; wire [3:0] A = {A3, A2, A1, A0}; xor(B[3], B3, M); xor(B[2], B2, M); xor(B[1], B1, M); xor(B[0], B0, M); xor (V, C, C3); ripple_carry_4_bit_adder M0 (Sum, C, C3, A, B, M); endmodule module t_supp_9_7c (); wire S3, S2, S1, S0, C, V; reg A3, A2, A1, A0, B3, B2, B1, B0, M; wire [3: 0] sum = {S3, S2, S1, S0}; wire [3: 0] A = {A3, A2, A1, A0}; wire [3: 0] B = {B3, B2, B1, B0}; supp_9_7c M0 (S3, S2, S1, S0, C, V, A3, A2, A1, A0, B3, B2, B1, B0, M); initial #2600 $finish; initial begin {A3, A2, A1, A0, B3, B2, B1, B0} = 0; M = 0; repeat (256) #5 {A3, A2, A1, A0, B3, B2, B1, B0} = {A3, A2, A1, A0, B3, B2, B1, B0} + 1; {A3, A2, A1, A0, B3, B2, B1, B0} = 0; M = 1; repeat (256) #5 {A3, A2, A1, A0, B3, B2, B1, B0} = {A3, A2, A1, A0, B3, B2, B1, B0} + 1; end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 379 module half_adder (output S, C, input x, y); // Instantiate primitive gates xor (S, x, y); and (C, x, y); endmodule // Verilog 2001, 2005 syntax module full_adder (output S, C, input x, y, z); wire S1, C1, C2; // Instantiate half adders half_adder HA1 (S1, C1, x, y); half_adder HA2 (S, C2, S1, z); or G1 (C, C2, C1); endmodule // Modify for C3 output module ripple_carry_4_bit_adder ( output [3: 0] Sum, output C4, C3, input [3:0] A, B, input C0); wire C1, C2; // Intermediate carries // Instantiate chain of full adders full_adder FA0 (Sum[0], C1, A[0], B[0], C0), FA1 (Sum[1], C2, A[1], B[1], C1), FA2 (Sum[2], C3, A[2], B[2], C2), FA3 (Sum[3], C4, A[3], B[3], C3); endmodule Addition: Name 312 332 352 3 A[3:0] B[3:0] 372 4 15 0 1 2 3 4 5 6 7 8 9 10 11 12 2 4 5 6 7 8 9 10 11 12 13 14 15 0 M sum[3:0] 1 C V Subtraction: Name 1740 1760 5 A[3:0] B[3:0] 1780 1800 6 12 13 14 9 8 7 15 0 1 2 3 4 5 6 7 8 9 5 4 3 2 1 0 15 14 13 M sum[3:0] 6 C V Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 380 Supplement to Experiment 8: (a) module Flip_flop_7474 (output reg Q, input D, CLK, preset, clear); always @ (posedge CLK, negedge preset , negedge clear) if (!preset) Q <= 1'b1; else if (!clear) Q <= 1'b0; else Q <= D; endmodule module t_Flip_flop_7474 (); wire Q; reg D, CLK, preset, clear; Flip_flop_7474 M0 (Q, D, CLK, preset, clear); initial #150 $finish; initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork preset = 0; clear = 0; #20 preset = 1; #40 clear = 1; join initial begin D = 0; #60 forever #20 D = ~D; end endmodule 0 60 Name 120 CLK preset clear D Q (b) //Solution to supplement Experiment 8(b) //Behavioral description of a 7474 D flip-flop with Q_not module Flip_Flop_7474_with_Q_not (output reg Q, Q_not, input D, CLK, Preset, Clear); always @ (posedge CLK, negedge Preset, negedge Clear) /* case ({Preset, Clear}) 2'b00: begin Q <= 1; Q_not <= 1; end 2'b01: begin Q <= 1; Q_not <= 0; end 2'b10: begin Q <= 0; Q_not <= 1; end 2'b11: begin Q <= D; Q_not <= ~D; end // NOTE: Q_not <= ~Q will produce a pipeline effect and delay Q_not by one clock endcase*/ if (Preset == 0) begin Q <= 1; if (Clear == 0) Q_not <= 1; else Q_not <= 0; end else if (Clear == 0) begin Q <= 0; Q_not <= 1; end else begin Q <= D; Q_not <= ~D; end Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 381 endmodule // Note: this model will not work if Preset and Clear are // both brought low and then high again. // A case statement for both Q and Q_not is also OK. module t_Flip_Flop_7474_with_Q_not (); wire Q, Q_not; reg D, CLK, Preset, Clear; Flip_Flop_7474_with_Q_not M0 (Q, Q_not, D, CLK, Preset, Clear); initial #250 $finish; initial begin CLK = 0; forever #5 CLK = ~CLK; end initial fork Preset = 1; Clear = 1; #50 Preset = 0; #80 Clear = Name 0 80 160 240 CLK Preset Clear D Q Q_not Supplement to Experiment #9: (a) module Figure_9_9a (output reg y, input x, clock, reset_b); reg [1: 0] state, next_state; parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; always @ (posedge clock, negedge reset_b) if (reset_b == 0) state <= S0; else state <= next_state; always @ (state, x) begin y = 0; case (state) S0: if (x) begin next_state = S0; y = 1; end else begin next_state = S1; y = 0; end S1: if (x) begin next_state = S3; y = 0; end else begin next_state = S2; y = 1; end S2: if (x) begin next_state = S1; y = 0; end else begin next_state = S0; y = 1; end S3: if (x) begin next_state = S2; y = 1; end else begin next_state = S3; y = 0; end endcase end endmodule module t_Figure_9_9a (); wire y; reg x, clock, reset_b; Figure_9_9a M0 (y, x, clock, reset_b); initial #200 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork reset_b = 0; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 382 x = 0; // S0. S1, S2 after release of reset_b #10 reset_b = 1; #40 x = 1; // Stay in S0 #60 x= 0; // S1, S2 #80 x = 1; // s1, S3, #100 x = 0; // S3 #130 x = 1; // S2, S1, S3 cycle join endmodule Name 0 60 120 180 clock reset_b x state[1:0] 0 1 2 0 1 2 1 3 2 1 3 2 1 3 y (b) The solution depends on the particular design. (c, d) Note: The HDL description of the state diagram produces outputs T0, T1, and T2. Additional logic must form the signals that control the datapath unit (Load_regs, Incr_P, Add_regs, and Shift_regs). An alternative controller that generates the control signals, rather than the states, as the outputs is given below too. It produces identical simulation results. module Supp_9_9cd # (parameter dp_width = 5) ( output [2*dp_width - 1: 0] Product, output Ready, input [dp_width - 1: 0] Multiplicand, Multiplier, input Start, clock, reset_b ); wire Load_regs, Incr_P, Add_regs, Shift_regs, Done, Q0; Controller M0 ( Ready, Load_regs, Incr_P, Add_regs, Shift_regs, Start, Done, Q0, clock, reset_b ); Datapath M1(Product, Q0, Done, Multiplicand, Multiplier, Start, Load_regs, Incr_P, Add_regs, Shift_regs, clock, reset_b); endmodule /* // This alternative controller directly produces the signals needed to control the datapath. module Controller ( output Ready, output reg Load_regs, Incr_P, Add_regs, Shift_regs, input Start, Done, Q0, clock, reset_b ); parameter S_idle = 3'b001, // one-hot code S_add = 3'b010, S_shift = 3'b100; reg [2: 0] state, next_state; // sized for one-hot assign Ready = (state == S_idle); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 383 always @ (posedge clock, negedge reset_b) if (~reset_b) state <= S_idle; else state <= next_state; always @ (state, Start, Q0, Done) begin next_state = S_idle; Load_regs = 0; Incr_P = 0; Add_regs = 0; Shift_regs = 0; case (state) S_idle: if (Start) begin next_state = S_add; Load_regs = 1; end S_add: begin next_state = S_shift; Incr_P = 1; if (Q0) Add_regs = 1; end S_shift: begin Shift_regs = 1; if (Done) next_state = S_idle; else next_state = S_add; end default: next_state = S_idle; endcase end endmodule */ // This controller has an embedded unit to generate T0, T1, and T2 and additional logic to form // // the signals needed to control the datapath. module Controller ( output Ready, Load_regs, Incr_P, Add_regs, Shift_regs, input Start, Done, Q0, clock, reset_b ); State_Generator M0 (T0, T1, T2, Start, Done, Q0, clock, reset_b); assign Ready = T0; assign Load_regs = T0 && Start; assign Incr_P = T1; assign Add_regs = T1 && Q0; assign Shift_regs = T2; endmodule module State_Generator (output T0,T1, T2, input Start, Done, Q0, clock, reset_b); parameter S_idle = 3'b001, // one-hot code S_add = 3'b010, S_shift = 3'b100; reg [2: 0] state, next_state; // sized for one-hot assign T0 = (state == S_idle); assign T1 = (state == S_add); assign T2 = (state == S_shift); always @ (posedge clock, negedge reset_b) if (~reset_b) state <= S_idle; else state <= next_state; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 384 always @ (state, Start, Q0, Done) begin next_state = S_idle; case (state) S_idle: if (Start) next_state = S_add; S_add: next_state = S_shift; S_shift: if (Done) next_state = S_idle; else next_state = S_add; default: next_state = S_idle; endcase end endmodule module Datapath #(parameter dp_width = 5, BC_size = 3) ( output [2*dp_width - 1: 0] Product, output Q0, output Done, input [dp_width - 1: 0] Multiplicand, Multiplier, input Start, Load_regs, Incr_P, Add_regs, Shift_regs, clock, reset_b ); // Default configuration: 5-bit datapath reg [dp_width - 1: 0] A, B, Q; // Sized for datapath reg C; reg [BC_size - 1: 0] P; // Bit counter assign Q0 = Q[0]; assign Done = (P == dp_width ); // Multiplier is exhausted assign Product = {C, A, Q}; always @ (posedge clock, negedge reset_b) if (reset_b == 0) begin // Added to this solution, but P <= 0; // not really necessary since Load_regs B <= 0; // initializes the datapath C <= 0; A <= 0; Q <= 0; end else begin if (Load_regs) begin P <= 0; A <= 0; C <= 0; B <= Multiplicand; Q <= Multiplier; end if (Add_regs) {C, A} <= A + B; if (Shift_regs) {C, A, Q} <= {C, A, Q} >> 1; if (Incr_P) P <= P+1 ; end endmodule module t_Supp_9_9cd; parameter wire [2 * dp_width - 1: 0] wire reg [dp_width - 1: 0] reg integer reg dp_width = 5; // Width of datapath Product; Ready; Multiplicand, Multiplier; Start, clock, reset_b; Exp_Value; Error; Supp_9_9cd M0(Product, Ready, Multiplicand, Multiplier, Start, clock, reset_b); initial #115000 $finish; initial begin clock = 0; #5 forever #5 clock = ~clock; end Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 385 initial fork reset_b = 1; #2 reset_b = 0; #3 reset_b = 1; join always @ (negedge Start) begin Exp_Value = Multiplier * Multiplicand; //Exp_Value = Multiplier * Multiplicand +1; end always @ (posedge Ready) begin # 1 Error <= (Exp_Value ^ Product) ; end // Inject error to confirm detection initial begin #5 Multiplicand = 0; Multiplier = 0; repeat (32) #10 begin Start = 1; #10 Start = 0; repeat (32) begin Start = 1; #10 Start = 0; #100 Multiplicand = Multiplicand + 1; end Multiplier = Multiplier + 1; end end endmodule Name 47359 47399 47439 47479 clock reset_b Ready Start Load_regs Add_regs Shift_regs Incr_P Q0 Done 1 state[2:0] 2 4 2 4 2 4 2 4 2 4 1 2 4 T0 T1 T2 Multiplicand[4:0] 11 12 13 13 Multiplier[4:0] Product[9:0] Exp_Value 143 143 13 397 198 99 483 241 625 312 156 13 156 Error Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 429 169 386 Supplement to Experiment #10: module Counter_74161 ( output QD, QC, QB, QA, output COUT, input D, C, B, A, input P, T, L, CK, CLR ); // Data output // Output carry // Data input // Active high to count // Active low to load // Positive edge sensitive // Active low to clear reg [3: 0] A_count; assign QD = A_count[3]; assign QC = A_count[2]; assign QB = A_count[1]; assign QA = A_count[0]; assign COUT = ((P == 1) && (T == 1) && (L == 1) && (A_count == 4'b1111)); always @ (posedge CK, negedge CLR) if (CLR == 0) A_count <= 4'b0000; else if (L == 0) A_count <= {D, C, B, A}; else if ((P == 1) && (T == 1)) A_count <= A_count + 1'b1; else A_count <= A_count; // redundant statement endmodule module t_Counter_74161 (); wire QD, QC, QB, QA; wire [3: 0] Data_outputs = {QD, QC, QB, QA}; wire Carry_out; // Output carry reg [3:0] Data_inputs; // Data input reg Count, // Active high to count Load, // Active low to load Clock, // Positive edge sensitive Clear; // Active low to clear Counter_74161 M0 (QD, QC, QB, QA, Carry_out, Data_inputs[3], Data_inputs[2], Data_inputs[1], Data_inputs[0], Count, Count, Load, Clock, Clear); initial #200 $finish; initial begin Clock = 0; forever #5 Clock = ~Clock; end initial fork Clear = 0; Load = 1; Count = 0; #20 Clear = 1; #40 Load = 0; #50 Load = 1; #80 Count = 1; #180 Count = 0; Data_inputs = 4'ha; join endmodule // 10 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 387 Name 0 70 140 Clock Clear Load Count a Data_inputs[3:0] Data_outputs[3:0] 0 a b c d e f 0 1 2 3 Supplement to Experiment #11. (a) // Note: J and K_bar are assumed to be connected together. module SReg_74195 ( output reg QA, QB, QC, QD, output QD_bar, input A, B, C, D, SH_LD, J, K_bar, CLR_bar, CK ); assign QD_bar = ~QD; always @ (posedge CK, negedge CLR_bar) if (!CLR_bar) {QA, QB, QC, QD} <= 4'b0; else if (!SH_LD) {QA, QB, QC, QD} <= {A, B, C, D}; else case ({J, K_bar}) 2'b00: {QA, QB, QC, QD} <= {1'b0, QA, QB, QC}; 2'b11: {QA, QB, QC, QD} <= {1'b1, QA, QB, QC}; 2'b01: {QA, QB, QC, QD} <= {QA, QA, QB, QC}; // unused 2'b10: {QA, QB, QC, QD} <= {~QA, QA, QB, QC}; // unused endcase endmodule module t_SReg_74195 (); wire QA, QB, QC, QD; wire QD_bar; reg A, B, C, D, SH_LD, CLR_bar, CK; reg Serial_Input; wire J = Serial_Input; wire K_bar = Serial_Input; wire [3: 0] Data_inputs = {A, B, C, D}; wire [3: 0] Data_outputs = {QA, QB, QC, QD}; SReg_74195 M0 (QA, QB, QC, QD, QD_bar, A, B, C, D, SH_LD, J, K_bar, CLR_bar, CK); initial #200 $finish; initial begin CK = 0; forever #5 CK = ~CK; end initial fork {A, B, C, D} = 4'ha; CLR_bar = 0; Serial_Input = 0; SH_LD = 0; #30 CLR_bar = 1; #60 SH_LD = 1; #120 Serial_Input = 1; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 4 388 Name 0 60 120 180 CK CLR_bar SH_LD Serial_Input A B C D QA QB QC QD QD_bar a Data_inputs[3:0] Data_outputs[3:0] 0 a 5 2 1 0 8 c e f Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 389 (b) module Mux_74157 ( output reg Y1, Y2, Y3, Y4, input A1, A2, A3, A4, B1, B2, B3, B4, SEL, STB ); wire [4: 1] In_A = {A1, A2, A3, A4}; wire [4: 1] In_B = {B1, B2, B3, B4}; always @ (In_A, In_B, SEL, STB) if (STB) {Y1, Y2, Y3, Y4} = 4'b0; else if (SEL) {Y1, Y2, Y3, Y4} = In_B; else {Y1, Y2, Y3, Y4} = In_A; endmodule module t_Mux_74157 (); wire Y1, Y2, Y3, Y4; reg A1, A2, A3, A4, B1, B2, B3, B4, SEL, STB; wire [4: 1] In_A = {A1, A2, A3, A4}; wire [4: 1] In_B = {B1, B2, B3, B4}; wire [4: 1] Y = {Y1, Y2, Y3, Y4}; Mux_74157 M0 (Y1, Y2, Y3, Y4, A1, A2, A3, A4, B1, B2, B3, B4, SEL, STB); initial #200 $finish; initial fork {A1, A2, A3, A4} = 4'ha; {B1, B2, B3, B4} = 4'hb; STB = 1; SEL = 1; #50 STB = 0; #100 SEL = 0; #150 STB = 1; join endmodule Name 0 60 120 In_A[4:1] a In_B[4:1] b 180 STB SEL Y[4:1] 0 b a 0 (c) module Bi_Dir_Shift_Reg (output [1: 4] D_out, input [1: 4] D_in, input SEL, STB, SH_LD, clock, CLR_bar); wire QD_bar; wire [1: 4] Y; SReg_74195 M0 (D_out[1], D_out[2], D_out[3], D_out[4], QD_bar, Y[1], Y[2], Y[3], Y[4], SH_LD, D_out[4], D_out[4], CLR_bar, clock ); Mux_74157 M1 (Y[1], Y[2], Y[3], Y[4], D_in[1], D_in[2], D_in[3], D_in[4], Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 390 D_out[2], D_out[3], D_out[4], D_out[1], SEL, STB ); endmodule module SReg_74195 ( output reg QA, QB, QC, QD, output QD_bar, input A, B, C, D, SH_LD, J, K_bar, CLR_bar, CK ); assign QD_bar = ~QD; always @ (posedge CK, negedge CLR_bar) if (!CLR_bar) {QA, QB, QC, QD} <= 4'b0; else if (!SH_LD) {QA, QB, QC, QD} <= {A, B, C, D}; else case ({J, K_bar}) 2'b00: {QA, QB, QC, QD} <= {1'b0, QA, QB, QC}; 2'b11: {QA, QB, QC, QD} <= {1'b1, QA, QB, QC}; 2'b01: {QA, QB, QC, QD} <= {QA, QA, QB, QC}; // unused 2'b10: {QA, QB, QC, QD} <= {~QA, QA, QB, QC}; // unused endcase endmodule module Mux_74157 ( output reg Y1, Y2, Y3, Y4, input A1, A2, A3, A4, B1, B2, B3, B4, SEL, STB ); wire [4: 1] In_A = {A1, A2, A3, A4}; wire [4: 1] In_B = {B1, B2, B3, B4}; always @ (In_A, In_B, SEL, STB) if (STB) {Y1, Y2, Y3, Y4} = 4'b0; else if (SEL) {Y1, Y2, Y3, Y4} = In_B; else {Y1, Y2, Y3, Y4} = In_A; endmodule // SEL = 1 // SEL = 0 module t_Bi_Dir_Shift_Reg (); wire [1: 4] D_out; reg [1: 4] D_in; reg SEL, STB, SH_LD, clock, CLR_bar; Bi_Dir_Shift_Reg M0 (D_out, D_in, SEL, STB, SH_LD, clock, CLR_bar); initial #200 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork D_in = 4'h8; // Data for walking 1 to right CLR_bar = 0; STB = 0; SEL = 0; // Selects D_in SH_LD = 0; // load D_in #10 CLR_bar = 1; #20 STB = 1; #40 STB = 0; #30 SH_LD = 1; #50 SH_LD = 0; // Interrupt count to load #60 SH_LD = 1; #80 SEL = 1; #100 STB = 1; #130 STB = 0; #140 SH_LD = 0; //#150 SH_LD = 1; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 391 Asynchronous clear Synchronous clear 60 0 Name No effect Reload 120 180 clock CLR_bar SH_LD STB SEL 8 D_in[1:4] 8 Y[1:4] D_out[1:4] 0 0 8 8 0 8 2 4 2 1 0 8 4 2 1 1 2 4 8 1 2 8 1 2 4 8 1 QD Shifting towards D_out[4] Shifting towards D_out[1] The behavioral model is listed below. The two models have matching simulation results. SH_LD SEL STB D_in[1: 4] D_out[ 4] 0 D_out[1: 4] 74157 74195 Parallel load 1 {D[2], D[3], D[4], D[1]} Note: CLR_b provides active-low asynchronous clear of D_out , overriding the functionality shown in the table below. SH_LD STB SEL 0 0 0 1 0 0 1 x 0 1 x x D_out <= D_in Shift_D_out towards D[1] (left) Synchronous clear: D_out <= 4'b0 Shift towards D_out[4] (right) module Bi_Dir_Shift_Reg_beh (output reg [1: 4] D_out, input [1: 4] D_in, input SEL, STB, SH_LD, clock, CLR_bar); always @ (posedge clock, negedge CLR_bar) if (!CLR_bar) D_out <= 4'b0; else if (SH_LD ) D_out <= {D_out[4], D_out[1], D_out[2], D_out[3]}; else if (!STB) D_out <= SEL ? {D_out[2: 4], D_out[1]}: D_in; else D_out <= 4'b0; endmodule module t_Bi_Dir_Shift_Reg_beh (); wire [1: 4] D_out; reg [1: 4] D_in; reg SEL, STB, SH_LD, clock, CLR_bar; Bi_Dir_Shift_Reg_beh M0 (D_out, D_in, SEL, STB, SH_LD, clock, CLR_bar); initial #200 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork D_in = 4'h8; // Data for walking 1 to right Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 392 CLR_bar = 0; STB = 0; SEL = 0; // Selects D_in SH_LD = 0; // load D_in #10 CLR_bar = 1; #20 STB = 1; #40 STB = 0; #30 SH_LD = 1; #50 SH_LD = 0; // Interrupt count to load #60 SH_LD = 1; #80 SEL = 1; #100 STB = 1; #130 STB = 0; #140 SH_LD = 0; //#150 SH_LD = 1; join endmodule Supplement to Experiment #13. module RAM_74189 (output S4, S3, S2, S1, input D4, D3, D2, D1, A3, A2, A1, A0, CS, WE); // Note: active-low CS and WE wire [3: 0] address = {A3, A2, A1, A0}; reg [3: 0] RAM [0: 15]; // 16 x 4 memory wire [4: 1] Data_in = { D4, D3, D2, D1}; // Input word tri [4: 1] Data; // Output data word, three-state output assign S1 = Data[1]; // Output bits assign S2 = Data[2]; assign S3 = Data[3]; assign S4 = Data[4]; always @ (Data_in, address, CS, WE) if (~CS && ~WE) RAM[address] = Data_in; assign Data = (~CS && WE) ? ~RAM[address] : 4'bz; endmodule module t_RAM_74189 (); reg [4: 1] Data_in; reg [3: 0] address; reg CS, WE; wire S1, S2, S3, S4; wire D1, D2, D3, D4; wire A0, A1, A2, A3; wire [4: 1] Data_out = {S4, S3, S2, S1}; assign D1 = Data_in [1]; assign D2 = Data_in [2]; assign D3 = Data_in [3]; assign D4 = Data_in [4]; assign A0 = address[0]; assign A1 = address[1]; assign A2 = address[2]; assign A3 = address[3]; wire [3: 0] RAM_0 = M0.RAM[0]; wire [3: 0] RAM_1 = M0.RAM[1]; wire [3: 0] RAM_2 = M0.RAM[2]; wire [3: 0] RAM_3 = M0.RAM[3]; wire [3: 0] RAM_4 = M0.RAM[4]; wire [3: 0] RAM_5 = M0.RAM[5]; wire [3: 0] RAM_6 = M0.RAM[6]; wire [3: 0] RAM_7 = M0.RAM[7]; wire [3: 0] RAM_8 = M0.RAM[8]; wire [3: 0] RAM_9 = M0.RAM[9]; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 393 wire [3: 0] RAM_10 = M0.RAM[10]; wire [3: 0] RAM_11 = M0.RAM[11]; wire [3: 0] RAM_12= M0.RAM[12]; wire [3: 0] RAM_13 = M0.RAM[13]; wire [3: 0] RAM_14 = M0.RAM[14]; wire [3: 0] RAM_15 = M0.RAM[15]; wire [4: 1] word = ~Data_out; RAM_74189 M0 (S4, S3, S2, S1, D4, D3, D2, D1, A3, A2, A1, A0, CS, WE); initial #110 $finish; initial fork WE = 1; CS = 1; address = 0; Data_in = 3; #10 CS = 0; #15 WE = 0; #20 WE = 1; #25 address = 14; #25 Data_in = 1; #30 WE = 0; #35 WE = 1; #40 CS = 1; #50 address = 0; #60 CS = 0; #70 CS = 1; #80 address = 14; #90 CS = 0; join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 394 Write Name Hi-Z 0 Read 30 60 90 CS WE address[3:0] 0 Data_in[4:1] 3 14 0 x RAM_0[3:0] 3 RAM_1[3:0] x RAM_2[3:0] x RAM_3[3:0] x RAM_4[3:0] x RAM_5[3:0] x RAM_6[3:0] x RAM_7[3:0] x RAM_8[3:0] x RAM_9[3:0] x RAM_10[3:0] x RAM_11[3:0] x RAM_12[3:0] x x RAM_13[3:0] x RAM_14[3:0] 1 x RAM_15[3:0] x word[4:1] Data_out[4:1] 14 1 z 3 x z 12 x x z 1 x 3 x 1 14 z 12 z 14 Note: Data_out is the complement of the stored value Supplement to Experiment #14. module Bi_Dir_Shift_Reg_74194 ( output reg QA, QB, QC, QD, input A, B, C, D, SIR, SIL, s1, s0, CK, CLR ); always @ (posedge CK, negedge CLR) if (!CLR) {QA, QB, QC, QD} <= 4'b0; else case ({s1, s0}) 2'b00: {QA, QB, QC, QD} <= {QA, QB, QC, QD}; 2'b01: {QA, QB, QC, QD} <= {SIR, QA, QB, QC}; 2'b10: {QA, QB, QC, QD} <= {QB, QC, QD, SIL}; 2'b11: {QA, QB, QC, QD} <= {A, B, C, D}; endcase endmodule module t_Bi_Dir_Shift_Reg_74194 (); wire QA, QB, QC, QD; reg A, B, C, D, SIR, SIL, s1, s0, clock, CLR; Bi_Dir_Shift_Reg_74194 M0 (QA, QB, QC, QD, A, B, C, D, SIR, SIL, s1, s0, clock, CLR); initial #250 $finish; initial begin clock = 0; forever #5 clock = ~clock; end Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 395 initial fork CLR = 0; {A, B, C, D} = 4'hf; s1 = 0; s0 = 0; SIL = 0; SIR = 0; #10 CLR = 1; #30 begin s1 = 1; s0 = 1; end// load #40 s1 = 0; // shift right #100 s1 = 1; // load #110 begin s1 = 0; s0 = 0; end #140 s1 = 1; // shift left #160 s1 = 0; // pause #180 s1 = 1; // resume join endmodule Load Load Shift right, filling 0 Shift left, filling 0 Pause Name 0 70 140 Shift left, filling 0 210 clock CLR s1 s0 A B C D SIR QA QB QC QD SIL Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 396 Supplement to Experiment #16. The HDL behavioral descriptions of the components in the block diagram of Fig. 9.23 are described in the solutions of previous experiments, along with their test benches and simulations results: 74189 is described in Experiment 13(a); 74157 in Experiment 11(b); 74161 in Experiment 10; 7483 in Experiment 7(a); 74194 in Experiment 14; and 7474 in Experiment 8(a). The structural description of the parallel adder instantiates these components to show how they are interconnected (see the solution to the supplement for Experiment 17 for a similar procedure). A test bench and simulation results for the integrated unit are given below. // LOAD condition for 74194: s1 = 1, s0 = 1 // SHIFT condition: s1 = 0, s0 = 1 // NO CHANGE condition: s1 = 0, s0 = 0 module Supp_9_16 ( output [3: 0] accum_sum, output carry, input [3: 0] Data_in, Addr_in, input SIR, SIL, CS, WE, s1, s0, count, Load, select, STB, clock, preset, clear, VCC, GND ); wire B4 = Data_in[3]; // Data world to memory wire B3 = Data_in[2]; wire B2 = Data_in[1]; wire B1 = Data_in[0]; wire S4, S3, S2, S1; wire D4, D3, D2, D1; wire S4b = ~S4; // Inverters wire S3b = ~S3; wire S2b = ~S2; wire S1b = ~S1; wire D = Addr_in[3]; // For parallel load of address counter wire C = Addr_in[2]; wire B = Addr_in[1]; wire A = Addr_in[0]; wire Ocar, Y1, Y2, Y3, Y4, QA, QB, QC, QD, A3, A2, A1, A0; assign accum_sum = {D4, D3, D2, D1}; Flip_flop_7474 M0 (Ocar, carry, clock, preset, clear); Adder_7483 M1 (D4, D3, D2, D1, carry, S4b, S3b, S2b, S1b, QD, QC, QB, QA, Ocar, VCC, GND); Mux_74157 M2 (Y4, Y3, Y2, Y1, QD, QC, QB, QA, B4, B3, B2, B1, select, STB); Counter_74161 M3 (A3, A2, A1, A0, COUT, D, C, B, A, count, count, Load, clock, clear); RAM_74189 M4 (S4, S3, S2, S1, Y4, Y3, Y2, Y1, A3, A2, A1, A0, CS, WE); Reg_74194 M5 (QD, QC, QB, QA, D4, D3, D2, D1, Ocar, SIL, s1, s0, clock, clear); endmodule module t_Supp_9_16 (); wire [3: 0] sum; wire carry; reg [3: 0] Data_in, Addr_in; reg SIR, SIL, CS, WE, s1, s0, count, Load, select, STB, clock, preset, clear; supply1 VCC; supply0 GND; wire [3: 0] RAM_0 = M0.M4.RAM[0]; wire [3: 0] RAM_1 = M0.M4.RAM[1]; wire [3: 0] RAM_2 = M0.M4.RAM[2]; wire [3: 0] RAM_3 = M0.M4.RAM[3]; wire [3: 0] RAM_4 = M0.M4.RAM[4]; wire [3: 0] RAM_5 = M0.M4.RAM[5]; wire [3: 0] RAM_6 = M0.M4.RAM[6]; wire [3: 0] RAM_7 = M0.M4.RAM[7]; wire [3: 0] RAM_8 = M0.M4.RAM[8]; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 397 wire [3: 0] RAM_9 = M0.M4.RAM[9]; wire [3: 0] RAM_10 = M0.M4.RAM[10]; wire [3: 0] RAM_11 = M0.M4.RAM[11]; wire [3: 0] RAM_12= M0.M4.RAM[12]; wire [3: 0] RAM_13 = M0.M4.RAM[13]; wire [3: 0] RAM_14 = M0.M4.RAM[14]; wire [3: 0] RAM_15 = M0.M4.RAM[15]; wire [4: 1] word = {M0.S4b, M0.S3b,M0.S2b, M0.S1b}; wire [4: 1] mux_out = { M0.Y4, M0.Y3, M0.Y2, M0.Y1}; wire [4: 1] Reg_Output = {M0.QD, M0.QC, M0.QB, M0.QA}; Supp_9_16 M0 (sum, carry, Data_in, Addr_in, SIR, SIL, CS, WE, s1, s0, count, Load, select, STB, clock, preset, clear, VCC, GND); integer k; initial #600 $finish; initial begin clock = 0; forever #5 clock = ~clock; end initial fork #10 begin preset = 1; clear = 0; s1 = 0; s0 = 0; Load = 1; count = 0; CS = 1; WE = 1; STB = 0; end // initialize memory #10 begin k = 0; repeat (16) begin M0.M4.RAM[k] = 4'hf; k = k + 1; end end #20 begin Data_in = 4'hf; Addr_in = 0; select = 1; end #30 begin clear = 1; WE = 0; end // load memory #40 begin count = 1; CS = 0; begin repeat (16) @ (negedge clock) Data_in = Data_in + 1; count = 0; @ (negedge clock) CS = 1; end end #200 count = 1; // Establish address #240 count = 0; #250 WE = 1; #260 CS = 0; // Read from memory #280 clear = 0; #290 clear = 1; #300 count = 1; // Establish address #340 begin s1 = 1; s0 = 1; count = 0; end #390 CS = 0; #400 clear = 0; // Clear the registers #410 clear = 1; #420 begin count = 1; CS = 0; end // Accumulate values #490 begin count = 0; CS = 1; end join endmodule module Flip_flop_7474 (output reg Q, input D, CLK, preset, clear); always @ (posedge CLK, negedge preset , negedge clear) if (!preset) Q <= 1'b1; else if (!clear) Q <= 1'b0; else Q <= D; endmodule module Adder_7483 ( output S4, S3, S2, S1, C4, Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 398 input A4, A3, A2, A1, B4, B3, B2, B1, C0, VCC, GND ); // Note: connect VCC and GND to supply1 and supply0 in the test bench wire [4: 1] sum; wire [4: 1] A = {A4, A3, A2, A1}; wire [4: 1] B = {B4, B3, B2, B1}; assign S4 = sum[4]; assign S3 = sum[3]; assign S2 = sum[2]; assign S1 = sum[1]; assign {C4, sum} = A + B + C0; endmodule module Mux_74157 ( output reg Y1, Y2, Y3, Y4, input A1, A2, A3, A4, B1, B2, B3, B4, SEL, STB ); wire [4: 1] In_A = {A1, A2, A3, A4}; wire [4: 1] In_B = {B1, B2, B3, B4}; always @ (In_A, In_B, SEL, STB) if (STB) {Y1, Y2, Y3, Y4} = 4'b0; else if (SEL) {Y1, Y2, Y3, Y4} = In_B; else {Y1, Y2, Y3, Y4} = In_A; endmodule module Counter_74161 ( output QD, QC, QB, QA, // Data output output COUT, // Output carry input D, C, B, A, // Data input input P, T, // Active high to count L, // Active low to load CK, // Positive edge sensitive CLR // Active low to clear ); reg [3: 0] A_count; assign QD = A_count[3]; assign QC = A_count[2]; assign QB = A_count[1]; assign QA = A_count[0]; assign COUT = ((P == 1) && (T == 1) && (L == 1) && (A_count == 4'b1111)); Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 399 always @ (posedge CK, negedge CLR) if (CLR == 0) A_count <= 4'b0000; else if (L == 0) A_count <= {D, C, B, A}; else if ((P == 1) && (T == 1)) A_count <= A_count + 1'b1; else A_count <= A_count; // redundant statement endmodule module RAM_74189 (output S4, S3, S2, S1, input D4, D3, D2, D1, A3, A2, A1, A0, CS, WE); // Note: active-low CS and WE wire [3: 0] address = {A3, A2, A1, A0}; reg [3: 0] RAM [0: 15]; // 16 x 4 memory wire [4: 1] Data_in = { D4, D3, D2, D1}; // Input word tri [4: 1] Data; // Output data word, three-state output assign S1 = Data[1]; // Output bits assign S2 = Data[2]; assign S3 = Data[3]; assign S4 = Data[4]; always @ (Data_in, address, CS, WE) if (~CS && ~WE) RAM[address] = Data_in; assign Data = (~CS && WE) ? ~RAM[address] : 4'bz; // Note complement of data word endmodule module Reg_74194 ( output reg QA, QB, QC, QD, input A, B, C, D, SIR, SIL, s1, s0, CK, CLR ); always @ (posedge CK, negedge CLR) if (!CLR) {QA, QB, QC, QD} <= 4'b0; else case ({s1, s0}) 2'b00: {QA, QB, QC, QD} <= {QA, QB, QC, QD}; 2'b01: {QA, QB, QC, QD} <= {SIR, QA, QB, QC}; 2'b10: {QA, QB, QC, QD} <= {QB, QC, QD, SIL}; 2'b11: {QA, QB, QC, QD} <= {A, B, C, D}; endcase endmodule Simulation results: initializing memory to 4'hf, then writing to memory. Note: the values of the inputs are ambiguous until the clear signal is asserted. Signals Ocar and carry are ambiguous because the output of memory is high-z until memory is read is read. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 400 Name 0 60 120 180 clock preset clear CS WE s1 s0 Load count select STB x Addr_in[3:0] address[3:0] 0 x 0 x Data_in[3:0] 1 f 0 2 1 3 2 4 5 3 6 4 5 6 8 7 9 8 10 9 11 a 12 b 13 c 14 d 15 e 0 f x word[4:1] Reg_Output[4:1] 7 x 0 Ocar x accum_sum[3:0] carry RAM_0[3:0] x RAM_1[3:0] x RAM_2[3:0] x RAM_3[3:0] x RAM_4[3:0] x RAM_5[3:0] x RAM_12[3:0] x RAM_13[3:0] x RAM_14[3:0] x RAM_15[3:0] x f 0 f 1 f 2 f 3 f 4 f 5 f c f d f e f Initialize memory f Write to memory Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 401 Sequence through addresses and accumulate the sum Clear registers Name 258 318 378 438 clock preset clear CS WE s1 s0 Load count select STB Addr_in[3:0] address[3:0] Data_in[3:0] word[4:1] Reg_Output[4:1] Ocar accum_sum[3:0] carry RAM_0[3:0] RAM_1[3:0] RAM_2[3:0] RAM_3[3:0] RAM_4[3:0] RAM_5[3:0] RAM_12[3:0] RAM_13[3:0] RAM_14[3:0] RAM_15[3:0] 0 3 0 1 2 3 4 0 1 f 3 0 1 2 3 0 x 0 1 2 3 4 4 8 4 12 0 5 0 8 12 0 5 9 1 0 0 0 1 2 3 4 5 c d e f Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 1 402 Clear registers Name Read and accumulate values 372 432 492 552 clock preset clear CS WE s1 s0 Load count select STB 0 Addr_in[3:0] 4 address[3:0] 0 1 2 3 5 6 7 f Data_in[3:0] 4 word[4:1] Reg_Output[4:1] 4 0 0 5 5 9 1 0 2 3 4 5 6 1 3 6 10 15 3 6 10 15 5 x 5 x Ocar accum_sum[3:0] 0 1 x carry RAM_0[3:0] 0 RAM_1[3:0] 1 RAM_2[3:0] 2 RAM_3[3:0] 3 RAM_4[3:0] 4 RAM_5[3:0] 5 RAM_12[3:0] c RAM_13[3:0] d RAM_14[3:0] e RAM_15[3:0] f Supplement to Experiment #17. The HDL behavioral descriptions of the components in the block diagram of Fig. 9.23 are described in the solutions of previous experiments, along with their test benches and simulations results: 74161 in Experiment 10; 7483 in Experiment 7(a); 74194 in Experiment 14; and 7474 in Experiment 8(a). The structural description of the parallel adder instantiates these components to show how they are interconnected (see the solution to the supplement for Experiment 17 for a similar procedure). A test bench and simulation results for the integrated unit are given below. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 403 // Control unit is obtained by modifying the solution to Prob. 8.24. // Datapath is implemented with a structural HDL model and IC components. // LOAD condition for 74194: s1 = 1, s0 = 1 // SHIFT condition: s1 = 0, s0 = 1 // NO CHANGE condition: s1 = 0, s0 = 0 module Supp_9_17_Par_Mult # (parameter dp_width = 4) ( output [2*dp_width - 1: 0] Product, output Ready, input [dp_width - 1: 0] Multiplicand, Multiplier, input Start, clock, reset_b, VCC, GND ); wire Load_regs, Incr_P, Add_regs, Shift_regs, Done, Q0; Controller M0 ( Ready, Load_regs, Incr_P, Add_regs, Shift_regs, Start, Done, Q0, clock, reset_b); Datapath M1(Product, Q0, Done, Multiplicand, Multiplier, Start, Load_regs, Incr_P, Add_regs, Shift_regs, clock, reset_b, VCC, GND); endmodule module Controller ( output Ready, output reg Load_regs, Incr_P, Add_regs, Shift_regs, input Start, Done, Q0, clock, reset_b ); parameter S_idle = 3'b001, // one-hot code S_add = 3'b010, S_shift = 3'b100; reg [2: 0] state, next_state; // sized for one-hot assign Ready = (state == S_idle); always @ (posedge clock, negedge reset_b) if (~reset_b) state <= S_idle; else state <= next_state; always @ (state, Start, Q0, Done) begin next_state = S_idle; Load_regs = 0; Incr_P = 0; Add_regs = 0; Shift_regs = 0; case (state) S_idle: if (Start) begin next_state = S_add; Load_regs = 1; end S_add: begin next_state = S_shift; Incr_P = 1; if (Q0) Add_regs = 1; end S_shift: begin Shift_regs = 1; if (Done) next_state = S_idle; else next_state = S_add; end default: next_state = S_idle; endcase end endmodule module Datapath #(parameter dp_width = 4, BC_size = 3) ( output [2*dp_width - 1: 0] Product, output Q0, output Done, input [dp_width - 1: 0] Multiplicand, Multiplier, input Start, Load_regs, Incr_P, Add_regs, Shift_regs, clock, clear, VCC, GND ); wire C; Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 404 wire Cout, Sum3, Sum2, Sum1, Sum0, P3, P2, P1, P0, A3, A2, A1, A0; wire Q3, Q2, Q1; wire [dp_width -1: 0] A = {A3, A2, A1, A0}; wire [dp_width -1: 0] Q = {Q3, Q2, Q1, Q0}; assign Product = {C, A, Q}; wire [ BC_size -1: 0] P = {P3, P2, P1, P0}; // Registers must be controlled separately to execute add and shift operations correctly. // LOAD condition for 74194: s1 = 1, s0 = 1 // SHIFT condition: s1 = 0, s0 = 1 // NO CHANGE condition: s1 = 0, s0 = 0 wire B3 = Multiplicand[3]; // Data word to adder wire B2 = Multiplicand[2]; wire B1 = Multiplicand[1]; wire B0 = Multiplicand[0]; wire Q3_in = Multiplier[3]; wire Q2_in = Multiplier[2]; wire Q1_in = Multiplier[1]; wire Q0_in = Multiplier[0]; assign Done = ({P3, P2, P1, P0} == dp_width); // Counts bits of multiplier wire s1A = Load_regs || Add_regs; // Controls for A register wire s0A = Load_regs || Add_regs || Shift_regs; wire s0Q = Load_regs || Shift_regs; // Controls for Q register wire s1Q = Load_regs; wire Pout; // Unused wire clr_P = clear && ~Load_regs; Flip_flop_7474 M0_C (C, Cout, clock, VCC, clr_P); Adder_7483 M1 (Sum3, Sum2, Sum1, Sum0, Cout, A3, A2, A1, A0, B3, B2, B1, B0, GND, VCC, GND); Counter_74161 M3_P (P3, P2, P1, P0, Pout, GND, GND, GND, GND, Incr_P, Incr_P, VCC, clock, clr_P); Reg_74194 M4_A (A3, A2, A1, A0, Sum3, Sum2, Sum1, Sum0, C, GND, s1A, s0A, clock, clr_P); Reg_74194 M5_Q (Q3, Q2, Q1, Q0, Q3_in, Q2_in, Q1_in, Q0_in, A0, GND, s1Q, s0Q, clock, clear); endmodule module t_Supp_9_17_Par_Mult; parameter dp_width = 4; // Width of datapath wire [2 * dp_width - 1: 0] Product; wire Ready; reg [dp_width - 1: 0] Multiplicand, Multiplier; reg Start, clock, reset_b; integer Exp_Value; reg Error; supply0 GND; supply1 VCC; Supp_11_17_Par_Mult M0 (Product, Ready, Multiplicand, Multiplier, Start, clock, reset_b, VCC, GND); wire [dp_width -1: 0] sum = {M0.M1.Sum3, M0.M1.Sum2, M0.M1.Sum1, M0.M1.Sum0}; initial #115000 $finish; initial begin clock = 0; #5 forever #5 clock = ~clock; end initial fork reset_b = 1; #2 reset_b = 0; #3 reset_b = 1; join always @ (negedge Start) begin Exp_Value = Multiplier * Multiplicand; //Exp_Value = Multiplier * Multiplicand +1; // Inject error to confirm detection end Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 405 always @ (posedge Ready) begin # 1 Error <= (Exp_Value ^ Product) ; end initial begin #5 Multiplicand = 0; Multiplier = 0; repeat (32) #10 begin Start = 1; #10 Start = 0; repeat (32) begin Start = 1; #10 Start = 0; #100 Multiplicand = Multiplicand + 1; end Multiplier = Multiplier + 1; end end endmodule module Flip_flop_7474 (output reg Q, input D, CLK, preset, clear); always @ (posedge CLK, negedge preset , negedge clear) if (!preset) Q <= 1'b1; else if (!clear) Q <= 1'b0; else Q <= D; endmodule module Adder_7483 ( output S4, S3, S2, S1, C4, input A4, A3, A2, A1, B4, B3, B2, B1, C0, VCC, GND ); // Note: connect VCC and GND to supply1 and supply0 in the test bench wire [4: 1] sum; wire [4: 1] A = {A4, A3, A2, A1}; wire [4: 1] B = {B4, B3, B2, B1}; assign S4 = sum[4]; assign S3 = sum[3]; assign S2 = sum[2]; assign S1 = sum[1]; assign {C4, sum} = A + B + C0; endmodule module Counter_74161 ( output QD, QC, QB, QA, // Data output output COUT, // Output carry input D, C, B, A, // Data input input P, T, // Active high to count L, // Active low to load CK, // Positive edge sensitive CLR // Active low to clear ); reg [3: 0] A_count; assign QD = A_count[3]; assign QC = A_count[2]; assign QB = A_count[1]; assign QA = A_count[0]; assign COUT = ((P == 1) && (T == 1) && (L == 1) && (A_count == 4'b1111)); always @ (posedge CK, negedge CLR) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 406 if (CLR == 0) A_count <= 4'b0000; else if (L == 0) A_count <= {D, C, B, A}; else if ((P == 1) && (T == 1)) A_count <= A_count + 1'b1; else A_count <= A_count; // redundant statement endmodule module Reg_74194 ( output reg QA, QB, QC, QD, input A, B, C, D, SIR, SIL, s1, s0, CK, CLR ); always @ (posedge CK, negedge CLR) if (!CLR) {QA, QB, QC, QD} <= 4'b0; else case ({s1, s0}) 2'b00: {QA, QB, QC, QD} <= {QA, QB, QC, QD}; 2'b01: {QA, QB, QC, QD} <= {SIR, QA, QB, QC}; 2'b10: {QA, QB, QC, QD} <= {QB, QC, QD, SIL}; 2'b11: {QA, QB, QC, QD} <= {A, B, C, D}; endcase endmodule Name 41353 41403 41453 41503 Ready Start Load_regs Shift_regs Add_regs Q0 s1A s0A s1Q s0Q Done state[2:0] 4 1 2 4 2 4 2 4 2 4 1 2 4 2 Incr_P clr_P 4 P[2:0] 0 1 2 3 4 0 1 C sum[3:0] A[3:0] 6 Q[3:0] f Multiplicand[3:0] 8 6 12 9 15 10 8 14 10 7 14 10 3 0 6 3 9 4 2 8 4 0 7 3 7 b 5 5 a 5 2 b 6 d 7 11 Multiplier[3:0] Product[7:0] 55 Exp_Value 55 11 53 74 37 66 11 66 Error Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 61 77 407 CHAPTER 10 10.1 7400 7404 1 2 3 & 4 6 8 12 13 11 1 4 3 =1 4 5 9 6 9 10 8 8 12 13 11 10 12 13 See textbook. 10.3 10.4 x y z G1 V2 N3 x y z A B C 1 2 3 A B C BCD-to-decimal decoder (similar to IC 7442) BCD/DEC A B C D 10.5 1 2 4 8 BIN-OCT 1 2 4 E3 10.6 0 1 2 3 4 5 6 7 8 9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Similar to 7438: E1 E2 6 5 11 10.2 1 2 3 5 9 10 7486 2 1 & EN 0 1 2 3 4 5 6 7 IC type 74153. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 408 s2 s1 0 1 } G 03 EN 1 2 MUX 4 EN 1 2 4 10.7 (a) (b) 1S C1 1R 1D C1 10.8 (c) 1T C1 The common control block is used when the circuit has one or more inputs that are common to all lower sections. 10.9 load clock M1 [Load] C2 I1 I2 I3 1, 2D A1 A2 A3 I4 10.10 A4 See textbook. 10.11 UP/DOWN COUNT ENABLE CLOCK CTR DIV 16 M1 [Up] M2 [Down] 1, 3 CT = 15 G3 2, 3 CT = 0 C/1, 3+/2,3- Carry out for count-up Carry out for count-down 0 CT 3 10.12 RAM 256 X 1 Address Select Read/Write Data input 0 1 2 0 3 A 255 4 5 6 7 G1 1EN [READ] 1C2 [WRITE] A, 2D Carry out for count-up Carry out for count-down Α Data output Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Source Exif Data:
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Digital Logic Design 5th Edition Solution Manual
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